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november 5, 1998 (version 5.2) 7-83 7 features ? low-cost, register/latch rich, sram based reprogrammable architecture -0.5 m m three-layer metal cmos process technology - 256 to 1936 logic cells (3,000 to 23,000 gates) - price competitive with gate arrays ? system level features - system performance beyond 50 mhz - 6 levels of interconnect hierarchy - versaring ? i/o interface for pin-locking - dedicated carry logic for high-speed arithmetic functions - cascade chain for wide input functions - built-in ieee 1149.1 jtag boundary scan test circuitry on all i/o pins - internal 3-state bussing capability - four dedicated low-skew clock or signal distribution nets ? versatile i/o and packaging - innovative versaring ? i/o interface provides a high logic cell to i/o ratio, with up to 244 i/o signals - programmable output slew-rate control maximizes performance and reduces noise - zero flip-flop hold time for input registers simplifies system timing - independent output enables for external bussing - footprint compatibility in common packages within the xc5200 series and with the xc4000 series - over 150 device/package combinations, including advanced bga, tq, and vq packaging available ? fully supported by xilinx development system - automatic place and route software - wide selection of pc and workstation platforms - over 100 3rd-party alliance interfaces - supported by shrink-wrap foundation software description the xc5200 field-programmable gate array family is engineered to deliver low cost. building on experiences gained with three previous successful sram fpga fami- lies, the xc5200 family brings a robust feature set to pro- grammable logic design. the versablock ? logic module, the versaring i/o interface, and a rich hierarchy of inter- connect resources combine to enhance design flexibility and reduce time-to-market. complete support for the xc5200 family is delivered through the familiar xilinx soft- ware environment. the xc5200 family is fully supported on popular workstation and pc platforms. popular design entry methods are fully supported, including abel, sche- matic capture, vhdl, and verilog hdl synthesis. design- ers utilizing logic synthesis can use their existing tools to design with the xc5200 devices. . 0 xc5200 series field programmable gate arrays november 5, 1998 (version 5.2) 07* product specification r table 1: xc5200 field-programmable gate array family members device xc5202 xc5204 xc5206 xc5210 xc5215 logic cells 256 480 784 1,296 1,936 max logic gates 3,000 6,000 10,000 16,000 23,000 typical gate range 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000 versablock array 8 x 8 10 x 12 14 x 14 18 x 18 22 x 22 clbs 64 120 196 324 484 flip-flops 256 480 784 1,296 1,936 i/os 84 124 148 196 244 tbufs per longline 1014162024
r xc5200 series field programmable gate arrays 7-84 november 5, 1998 (version 5.2) xc5200 family compared to xc4000/spartan? and xc3000 series for readers already familiar with the xc4000/spartan and xc3000 fpga families, this section describes significant differences between them and the xc5200 family. unless otherwise indicated, comparisons refer to both xc4000/spartan and xc3000 devices. configurable logic block (clb) resources each xc5200 clb contains four independent 4-input func- tion generators and four registers, which are configured as four independent logic cells? (lcs). the registers in each xc5200 lc are optionally configurable as edge-triggered d-type flip-flops or as transparent level-sensitive latches. the xc5200 clb includes dedicated carry logic that pro- vides fast arithmetic carry capability. the dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions. xc4000 family: xc5200 devices have no wide edge decoders. wide decoders are implemented using cascade logic. although sacrificing speed for some designs, lack of wide edge decoders reduces the die area and hence cost of the xc5200. xc4000/spartan family: xc5200 dedicated carry logic differs from that of the xc4000/spartan family in that the sum is generated in an additional function generator in the adjacent column. this design reduces xc5200 die size and hence cost for many applications. note, however, that a loadable up/down counter requires the same number of function generators in both families. xc3000 has no dedi- cated carry. xc4000/spartan family: xc5200 lookup tables are opti- mized for cost and hence cannot implement ram. input/output block (iob) resources the xc5200 family maintains footprint compatibility with the xc4000 family, but not with the xc3000 family. to minimize cost and maximize the number of i/o per logic cell, the xc5200 i/o does not include flip-flops or latches. for high performance paths, the xc5200 family provides direct connections from each iob to the registers in the adjacent clb in order to emulate iob registers. each xc5200 i/o pin provides a programmable delay ele- ment to control input set-up time. this element can be used to avoid potential hold-time problems. each xc5200 i/o pin is capable of 8-ma source and sink currents. ieee 1149.1-type boundary scan is supported in each xc5200 i/o. routing resources the xc5200 family provides a flexible coupling of logic and local routing resources called the versablock. the xc5200 versablock element includes the clb, a local interconnect matrix (lim), and direct connects to neighboring versa- blocks. the xc5200 provides four global buffers for clocking or high-fanout control signals. each buffer may be sourced by means of its dedicated pad or from any internal source. each xc5200 tbuf can drive up to two horizontal and two vertical longlines. there are no internal pull-ups for xc5200 longlines. configuration and readback the xc5200 supports a new configuration mode called express mode. xc4000/spartan family: the xc5200 family provides a global reset but not a global set. xc5200 devices use a different configuration process than that of the xc3000 family, but use the same process as the xc4000 and spartan families. xc3000 family: although their configuration processes dif- fer, xc5200 devices may be used in daisy chains with xc3000 devices. xc3000 family: the xc5200 program pin is a sin- gle-function input pin that overrides all other inputs. the program pin does not exist in xc3000. table 2: xilinx field-programmable gate array families parameter xc5200 spartan xc4000 xc3000 clb function generators 4332 clb inputs 20 9 9 5 clb outputs 12 4 4 2 global buffers 4 8 8 2 user ram no yes yes no edge decoders no no yes no cascade chain yes no no no fast carry logic yes yes yes no internal 3-state yes yes yes yes boundary scan yes yes yes no slew-rate control yes yes yes yes
r november 5, 1998 (version 5.2) 7-85 xc5200 series field programmable gate arrays 7 xc3000 family: xc5200 devices support an additional pro- gramming mode: peripheral synchronous. xc3000 family: the xc5200 family does not support power-down, but offers a global 3-state input that does not reset any flip-flops. xc3000 family: the xc5200 family does not provide an on-chip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 12 mhz are available. architectural overview figure 1 presents a simplified, conceptual overview of the xc5200 architecture. similar to conventional fpgas, the xc5200 family consists of programmable iobs, program- mable logic blocks, and programmable interconnect. unlike other fpgas, however, the logic and local routing resources of the xc5200 family are combined in flexible versablocks ( figure 2 ). general-purpose routing connects to the versablock through the general routing matrix (grm). versablock: abundant local routing plus versatile logic the basic logic element in each versablock structure is the logic cell, shown in figure 3 . each lc contains a 4-input function generator (f), a storage device (fd), and control logic. there are five independent inputs and three outputs to each lc. the independence of the inputs and outputs allows the software to maximize the resource utilization within each lc. each logic cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for fpgas. the storage device is configurable as either a d flip-flop or a latch. the control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions. figure 1: xc5200 architectural overview figure 2: versablock figure 3: xc5200 logic cell (four lcs per clb) x4955 grm input/output blocks (iobs) versa- block grm versa- block versaring versaring grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block versaring versaring x5707 clb direct connects ts grm lim 4 4 4 4 4 lc3 lc2 lc1 lc0 4 4 44 24 24 x4956 f4 f3 f fd f2 f1 dq x do di co ci ce ck clr
r xc5200 series field programmable gate arrays 7-86 november 5, 1998 (version 5.2) the xc5200 clb consists of four lcs, as shown in figure 4 . each clb has 20 independent inputs and 12 independent outputs. the top and bottom pairs of lcs can be configured to implement 5-input functions. the chal- lenge of fpga implementation software has always been to maximize the usage of logic resources. the xc5200 family addresses this issue by surrounding each clb with two types of local interconnect the local interconnect matrix (lim) and direct connects. these two interconnect resources, combined with the clb, form the versablock, represented in figure 2 . the lim provides 100% connectivity of the inputs and out- puts of each lc in a given clb. the benefit of the lim is that no general routing resources are required to connect feedback paths within a clb. the lim connects to the grm via 24 bidirectional nodes. the direct connects allow immediate connections to neigh- boring clbs, once again without using any of the general interconnect. these two layers of local routing resource improve the granularity of the architecture, effectively mak- ing the xc5200 family a sea of logic cells. each versa-block has four 3-state buffers that share a common enable line and directly drive horizontal and vertical lon- glines, creating robust on-chip bussing capability. the versablock allows fast, local implementation of logic func- tions, effectively implementing user designs in a hierarchi- cal fashion. these resources also minimize local routing congestion and improve the efficiency of the general inter- connect, which is used for connecting larger groups of logic. it is this combination of both fine-grain and coarse-grain architecture attributes that maximize logic uti- lization in the xc5200 family. this symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with mini- mal routing restrictions. versaring i/o interface the interface between the iobs and core logic has been redesigned in the xc5200 family. the iobs are completely decoupled from the core logic. the xc5200 iobs contain dedicated boundary-scan logic for added board-level test- ability, but do not include input or output registers. this approach allows a maximum number of iobs to be placed around the device, improving the i/o-to-gate ratio and decreasing the cost per i/o. a freeway of interconnect cells surrounding the device forms the versaring, which provides connections from the iobs to the internal logic. these incremental routing resources provide abundant connections from each iob to the nearest versablock, in addition to longline connections surrounding the device. the versaring eliminates the historic trade-off between high logic utilization and pin placement flexibility. these incremental edge resources give users increased flexibility in preassigning (i.e., locking) i/o pins before completing their logic designs. this ability accelerates time-to-market, since pcbs and other system components can be manu- factured concurrent with the logic design. general routing matrix the grm is functionally similar to the switch matrices found in other architectures, but it is novel in its tight cou- pling to the logic resources contained in the versablocks. advanced simulation tools were used during the develop- ment of the xc5200 architecture to determine the optimal level of routing resources required. the xc5200 family contains six levels of interconnect hierarchy a series of figure 4: configurable logic block x4957 f4 f3 f fd lc3 lc2 lc1 lc0 f2 f1 dq x do di co f4 f3 f fd f2 f1 dq x do di f4 f3 f fd f2 f1 dq x do di f4 f3 f fd f2 f1 dq x do di ci ce ck clr lc0
r november 5, 1998 (version 5.2) 7-87 xc5200 series field programmable gate arrays 7 single-length lines, double-length lines, and longlines all routed through the grm. the direct connects, lim, and logic-cell feedthrough are contained within each versa-block. throughout the xc5200 interconnect, an effi- cient multiplexing scheme, in combination with three layer metal (tlm), was used to improve the overall efficiency of silicon usage. performance overview the xc5200 family has been benchmarked with many designs running synchronous clock rates beyond 66 mhz. the performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the intercon- nect routing. a rough estimate of timing can be made by assuming 3-6 ns per logic level, which includes direct-con- nect routing delays, depending on speed grade. more accurate estimations can be made using the information in the switching characteristic guideline section. taking advantage of reconfiguration fpga devices can be reconfigured to change logic function while resident in the system. this capability gives the sys- tem designer a new degree of freedom not available with any other type of logic. hardware can be changed as easily as software. design updates or modifications are easy, and can be made to products already in the field. an fpga can even be recon- figured dynamically to perform different functions at differ- ent times. reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfig- ured for different environments or operations, or implement multi-purpose hardware for a given application. as an added benefit, using reconfigurable fpga devices simpli- fies hardware design and debugging and shortens product time-to-market. detailed functional description configurable logic blocks (clbs) figure 4 shows the logic in the xc5200 clb, which con- sists of four logic cells (lc[3:0]). each logic cell consists of an independent 4-input lookup table (lut), and a d-type flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. addi- tional logic features provided in the clb are: ? an independent 5-input lut by combining two 4-input luts. ? high-speed carry propagate logic. ? high-speed pattern decoding. ? high-speed direct connection to flip-flop d-inputs. ? individual selection of either a transparent, level-sensitive latch or a d flip-flop. ? four 3-state buffers with a shared output enable. 5-input functions figure 5 illustrates how the outputs from the luts from lc0 and lc1 can be combined with a 2:1 multiplexer (f5_mux) to provide a 5-input function. the outputs from the luts of lc2 and lc3 can be similarly combined. figure 5: two luts in parallel combined to create a 5-input function out q qout do q d fd x fd co di x clr lc0 ck ce 5-input function d do f5_mux di f f4 f3 f2 f1 f4 f3 f2 f1 i1 i2 i3 i4 i5 ci f lc1 x5710
r xc5200 series field programmable gate arrays 7-88 november 5, 1998 (version 5.2) carry function the xc5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. a carry multiplexer (cy_mux) sym- bol is used to indicate the xc5200 carry logic. this symbol represents the dedicated 2:1 multiplexer in each lc that performs the one-bit high-speed carry propagate per logic cell (four bits per clb). while the carry propagate is performed inside the lc, an adjacent lc must be used to complete the arithmetic func- tion. figure 6 represents an example of an adder function. the carry propagate is performed on the clb shown, which also generates the half-sum for the four-bit adder. an adjacent clb is responsible for xoring the half-sum with the corresponding carry-out. thus an adder or counter requires two lcs per bit. notice that the carry chain requires an initialization stage, which the xc5200 family accomplishes using the carry initialize (cy_init) macro and one additional lc. the carry chain can propagate ver- tically up a column of clbs. the xc5200 library contains a set of relationally-placed macros (rpms) and arithmetic functions designed to take advantage of the dedicated carry logic. using and modify- ing these macros makes it much easier to implement cus- figure 6: xc5200 cy_mux used for adder carry propagate f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 xor xor xor xor f=0 di di di di fd fd fd fd carry out carry3 do d x lc3 do dq lc2 x ci carry in cy_mux cy_mux cy_mux cy_mux cy_mux x do do do do lc1 lc0 ck ce clr d d q q x q half sum0 carry0 half sum2 half sum1 carry1 carry2 half sum3 co a3 or b3 a3 and b3 to any two a2 and b2 to any two a2 or b2 a1 or b1 a1 and b1 to any two a0 or b0 a0 and b0 to any two 0 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 xor xor xor xor di di di di fd fd do fd fd d x lc3 do dq lc2 x ci x lc1 lc0 ck ce clr d d q q x q sum0 sum2 sum1 sum3 co initialization of carry chain (one logic cell) x5709
r november 5, 1998 (version 5.2) 7-89 xc5200 series field programmable gate arrays 7 tomized rpms, freeing the designer from the need to become an expert on architectures. cascade function each cy_mux can be connected to the cy_mux in the adjacent lc to provide cascadable decode logic. figure 7 illustrates how the 4-input function generators can be con- figured to take advantage of these four cascaded cy_muxes. note that and and or cascading are specific cases of a general decode. in and cascading all bits are decoded equal to logic one, while in or cascading all bits are decoded equal to logic zero. the flexibility of the lut achieves this result. the xc5200 library contains gate macros designed to take advantage of this function. clb flip-flops and latches the clb can pass the combinatorial output(s) to the inter- connect network, but can also store the combinatorial results or other incoming data in flip-flops, and connect their outputs to the interconnect network as well. the clb storage elements can also be configured as latches. data inputs and outputs the source of a storage element data input is programma- ble. it is driven by the function f, or by the direct in (di) block input. the flip-flops or latches drive the q clb out- puts. four fast feed-through paths from di to do are available, as shown in figure 4 . this bypass is sometimes used by the automated router to repower internal signals. in addi- tion to the storage element (q) and direct (do) outputs, there is a combinatorial output (x) that is always sourced by the lookup table. the four edge-triggered d-type flip-flops or level-sensitive latches have common clock (ck) and clock enable (ce) inputs. any of the clock inputs can also be permanently enabled. storage element functionality is described in tab le 3 . clock input the flip-flops can be triggered on either the rising or falling clock edge. the clock pin is shared by all four storage ele- ments with individual polarity control. any inverter placed on the clock input is automatically absorbed into the clb. clock enable the clock enable signal (ce) is active high. the ce pin is shared by the four storage elements. if left unconnected for any, the clock enable for that storage element defaults to the active state. ce is not invertible within the clb. clear an asynchronous storage element input (clr) can be used to reset all four flip-flops or latches in the clb. this input figure 7: xc5200 cy_mux used for decoder cascade logic f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 f4 f3 f2 f1 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 and and f=0 di di di di fd fd fd cascade out out do d x lc3 do do do dq lc2 x ci cascade in cy_mux cy_mux cy_mux cy_mux cy_mux fd x lc1 initialization of carry chain (one logic cell) lc0 ck ce clr d d q q x q co and and x5708 table 3: clb storage element functionality (active rising edge is shown) mode ck ce clr d q power-up or gr xxxx0 flip-flop xx1x0 __/ 1* 0* d d 0x0*xq latch 11*0*xq 01*0*dd both x 0 0* x q legend: x __/ 0* 1* dont care rising edge input is low or unconnected (default value) input is high or unconnected (default value)
r xc5200 series field programmable gate arrays 7-90 november 5, 1998 (version 5.2) can also be independently disabled for any flip-flop. clr is active high. it is not invertible within the clb. global reset a separate global reset line clears each storage element during power-up, reconfiguration, or when a dedicated reset net is driven active. this global net (gr) does not compete with other routing resources; it uses a dedicated distribution network. gr can be driven from any user-programmable pin as a global reset input. to use this global net, place an input pad and input buffer in the schematic or hdl code, driving the gr pin of the startup symbol. (see figure 9 .) a specific pin location can be assigned to this input using a loc attribute or property, just as with any other user-program- mable pad. an inverter can optionally be inserted after the input buffer to invert the sense of the global reset signal. alternatively, gr can be driven from any internal node. using fpga flip-flops and latches the abundance of flip-flops in the xc5200 series invites pipelined designs. this is a powerful way of increasing per- formance by breaking the function into smaller subfunc- tions and executing them in parallel, passing on the results through pipeline flip-flops. this method should be seriously considered wherever throughput is more important than latency. to include a clb flip-flop, place the appropriate library symbol. for example, fdce is a d-type flip-flop with clock enable and asynchronous clear. the corresponding latch symbol is called ldce. in xc5200-series devices, the flip-flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task. this ability increases the functional capacity of the devices. the clb setup time is specified between the function gen- erator inputs and the clock input ck. therefore, the speci- fied clb flip-flop setup time includes the delay through the function generator. three-state buffers the xc5200 family has four dedicated three-state buffers (tbufs, or bufts in the schematic library) per clb (see figure 9 ). the four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. when in 3-state mode the clb output enable (ts) control signal drives the enable to all four buffers. each tbuf can drive up to two horizontal and/or two vertical longlines. these 3-state buff- ers can be used to implement multiplexed or bidirectional buses on the horizontal or vertical longlines, saving logic resources. the 3-state buffer enable is an active-high 3-state (i.e. an active-low enable), as shown in ta b l e 4 . another 3-state buffer with similar access is located near each i/o block along the right and left edges of the array. the longlines driven by the 3-state buffers have a weak keeper at each end. this circuit prevents undefined float- ing levels. however, it is overridden by any driver. to ensure the longline goes high when no buffers are on, add an additional buft to drive the output high during all of the previously undefined states. figure 10 shows how to use the 3-state buffers to imple- ment a multiplexer. the selection is accomplished by the buffer 3-state signal. pad ibuf gr gts clk donein q1q4 q2 q3 startup x9009 figure 8: schematic symbols for global reset table 4: three-state buffer functionality in t out x1z in 0 in clb ts lc3 lc2 lc1 lc0 clb horizontal longlines x9030 figure 9: xc5200 3-state buffers
r november 5, 1998 (version 5.2) 7-91 xc5200 series field programmable gate arrays 7 input/output blocks user-configurable input/output blocks (iobs) provide the interface between external package pins and the internal logic. each iob controls one package pin and can be con- figured for input, output, or bidirectional signals. the i/o block, shown in figure 11 , consists of an input buffer and an output buffer. the output driver is an 8-ma full-rail cmos buffer with 3-state control. two slew-rate control modes are supported to minimize bus transients. both the output buffer and the 3-state control are invertible. the input buffer has globally selected cmos or ttl input thresholds. the input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set-up and hold times. minimum esd protection is 3 kv using the human body model. iob input signals the xc5200 inputs can be globally configured for either ttl (1.2v) or cmos thresholds, using an option in the bit- stream generation software. there is a slight hysteresis of about 300mv. the inputs of xc5200-series 5-volt devices can be driven by the outputs of any 3.3-volt device, if the 5-volt inputs are in ttl mode. supported sources for xc5200-series device inputs are shown in tab le 5 . optional delay guarantees zero hold time xc5200 devices do not have storage elements in the iobs. however, xc5200 iobs can be efficiently routed to clb flip-flops or latches to store the i/o signals. the data input to the register can optionally be delayed by several nanoseconds. with the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. a positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. the input flip-flop setup time is defined between the data measured at the device i/o pin and the clock input at the clb (not at the clock pin). any routing delay from the device clock pin to the clock input of the clb must, there- fore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. a short specified setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. when a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. the maxi- mum delay is therefore inserted as the software default. the xc5200 iob has a one-tap delay element: either the delay is inserted (default), or it is not. the delay guarantees a zero hold time with respect to clocks routed through any of the xc5200 global clock buffers. (see global lines on page 96 for a description of the global clock buffers in the xc5200.) for a shorter input register setup time, with d n d c d b d a abcn z = d a ?a + d b ?b + d c ?c + d n ?n ~100 k w "weak keeper" x6466 buft buft buft buft figure 10: 3-state buffers implement a multiplexer figure 11: xc5200 i/o block i o t pad vcc x9001 input buffer delay pullup pulldown slew rate control output buffer table 5: supported sources for xc5200-series device inputs source xc5200 input mode 5 v, ttl 5 v, cmos any device, vcc = 3.3 v, cmos outputs ? unreliable data any device, vcc = 5 v, ttl outputs ? any device, vcc = 5 v, cmos outputs ??
r xc5200 series field programmable gate arrays 7-92 november 5, 1998 (version 5.2) non-zero hold, attach a nodelay attribute or property to the flip-flop or input buffer. iob output signals output signals can be optionally inverted within the iob, and pass directly to the pad. as with the inputs, a clb flip-flop or latch can be used to store the output signal. an active-high 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional i/o. under configuration control, the output (out) and output 3-state (t) signals can be inverted. the polarity of these signals is independently configured for each iob. the xc5200 devices provide a guaranteed output sink cur- rent of 8 ma. supported destinations for xc5200-series device outputs are shown in ta b l e 6 .(for a detailed discussion of how to interface between 5 v and 3.3 v devices, see the 3v prod- ucts section of the programmable logic data book .) an output can be configured as open-drain (open-collector) by placing an obuft symbol in a schematic or hdl code, then tying the 3-state pin (t) to the output signal, and the input pin (i) to ground. (see figure 12 .) table 6: supported destinations for xc5200-series outputs output slew rate the slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. for critical signals, attach a fast attribute or property to the output buffer or flip-flop. for xc5200 devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pf for all package pins between each power/ground pin pair. for some xc5200 devices, additional internal power/ground pin pairs are connected to special power and ground planes within the packages, to reduce ground bounce. for slew-rate limited outputs this total is two times larger for each device type: 400 pf for xc5200 devices. this maxi- mum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 v amplitude and more than 5 ns duration. this level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. this restriction is common to all high-speed digital ics, and is not particular to xilinx or the xc5200 series. xc5200-series devices have a feature called soft start-up, designed to reduce ground bounce when all out- puts are turned on simultaneously at the end of configura- tion. when the configuration process is finished and the device starts up, the first activation of the outputs is auto- matically slew-rate limited. immediately following the initial activation of the i/o, the slew rate of the individual outputs is determined by the individual configuration option for each iob. global three-state a separate global 3-state line (not shown in figure 11 ) forces all fpga outputs to the high-impedance state, unless boundary scan is enabled and is executing an extest instruction. this global net (gts) does not com- pete with other routing resources; it uses a dedicated distri- bution network. gts can be driven from any user-programmable pin as a global 3-state input. to use this global net, place an input pad and input buffer in the schematic or hdl code, driving the gts pin of the startup symbol. a specific pin loca- tion can be assigned to this input using a loc attribute or property, just as with any other user-programmable pad. an inverter can optionally be inserted after the input buffer to invert the sense of the global 3-state signal. using gts is similar to global reset. see figure 8 on page 90 for details. alternatively, gts can be driven from any internal node. other iob options there are a number of other programmable options in the xc5200-series iob. pull-up and pull-down resistors programmable iob pull-up and pull-down resistors are useful for tying unused pins to vcc or ground to minimize power consumption and reduce noise sensitivity. the con- figurable pull-up resistor is a p-channel transistor that pulls destination xc5200 output mode 5 v, cmos xc5200 device, v cc =3.3 v, cmos-threshold inputs ? any typical device, v cc = 3.3 v, cmos-threshold inputs some 1 1. only if destination device has 5-v tolerant inputs any device, v cc = 5 v, ttl-threshold inputs ? any device, v cc = 5 v, cmos-threshold inputs ? x6702 opad obuft figure 12: open-drain output
r november 5, 1998 (version 5.2) 7-93 xc5200 series field programmable gate arrays 7 to vcc. the configurable pull-down resistor is an n-channel transistor that pulls to ground. the value of these resistors is 20 k w - 100 k w . this high value makes them unsuitable as wired-and pull-up resis- tors. the pull-up resistors for most user-programmable iobs are active during the configuration process. see table 13 on page 124 for a list of pins with pull-ups active before and during configuration. after configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. therefore, by default, unused pads are configured with the internal pull-up resis- tor active. alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. to activate the internal pull-up, attach the pullup library component to the net attached to the pad. to activate the internal pull-down, attach the pulldown library component to the net attached to the pad. jtag support embedded logic attached to the iobs contains test struc- tures compatible with ieee standard 1149.1 for boundary scan testing, simplifying board-level testing. more informa- tion is provided in boundary scan on page 98 . oscillator xc5200 devices include an internal oscillator. this oscilla- tor is used to clock the power-on time-out, clear configura- tion memory, and source cclk in master configuration modes. the oscillator runs at a nominal 12 mhz frequency that varies with process, vcc, and temperature. the output cclk frequency is selectable as 1 mhz (default), 6 mhz, or 12 mhz. the xc5200 oscillator divides the internal 12-mhz clock or a user clock. the user then has the choice of dividing by 4, 16, 64, or 256 for the osc1 output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the osc2 out- put. the division is specified via a dividen_by=x attribute on the symbol, where n=1 for osc1, or n=2 for osc2. these frequencies can vary by as much as -50% or + 50%. the osc5 macro is used where an internal oscillator is required. the ck_div macro is applicable when a user clock input is specified (see figure 13 ). versablock routing the general routing matrix (grm) connects to the versa-block via 24 bidirectional ports (m0-m23). excluding direct connections, global nets, and 3-statable longlines, all versablock inputs and outputs connect to the grm via these 24 ports. four 3-statable unidirectional signals (tq0-tq3) drive out of the versablock directly onto the horizontal and vertical longlines. two horizontal global nets and two vertical global nets connect directly to every clb clock pin; they can connect to other clb inputs via the grm. each clb also has four unidirectional direct con- nects to each of its four neighboring clbs. these direct connects can also feed directly back to the clb (see figure 14 ). in addition, each clb has 16 direct inputs, four direct con- nections from each of the neighboring clbs. these direct connections provide high-speed local routing that bypasses the grm. local interconnect matrix the local interconnect matrix (lim) is built from input and output multiplexers. the 13 clb outputs (12 lc outputs plus a v cc /gnd signal) connect to the eight versablock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. of the eight versablock outputs, four signals drive each neighboring clb directly, and provide a direct feedback path to the input multiplexers. the four remaining multiplexer outputs can drive the grm through four tbufs (tq0-tq3). all eight multiplexer outputs can connect to the grm through the bidirectional m0-m23 signals. all eight signals also connect to the input multiplexers and are potential inputs to that clb. oscs ck_div osc1 osc1 osc2 osc2 5200_14 figure 13: xc5200 oscillator macros
r xc5200 series field programmable gate arrays 7-94 november 5, 1998 (version 5.2) clb inputs have several possible sources: the 24 signals from the grm, 16 direct connections from neighboring versablocks, four signals from global, low-skew buffers, and the four signals from the clb output multiplexers. unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available sig- nals can be connected to a given clb input. the flexibility of lut input swapping and lut mapping compensates for this limitation. for example, if a 2-input nand gate is required, it can be mapped into any of the four luts, and use any two of the four inputs to the lut. direct connects the unidirectional direct-connect segments are connected to the logic input/output pins through the clb input and out- put multiplexer arrays, and thus bypass the general routing matrix altogether. these lines increase the routing channel utilization, while simultaneously reducing the delay incurred in speed-critical connections. the direct connects also provide a high-speed path from the edge clbs to the versaring input/output buffers, and thus reduce pin-to-pin set-up time, clock-to-out, and combi- national propagation delay. direct connects from the input buffers to the clb di pin (direct flip-flop input) are only available on the left and right edges of the device. clb look-up table inputs and combinatorial/registered outputs have direct connects to input/output buffers on all four sides. the direct connects are ideal for developing customized rpm cells. using direct connects improves the macro per- formance, and leaves the other routing channels intact for improved routing. direct connects can also route through a clb using one of the four cell-feedthrough paths. general routing matrix the general routing matrix, shown in figure 15 , provides flexible bidirectional connections to the local interconnect figure 14: versablock details 4 4 4 4 5 5 5 5 3 3 3 3 24 to grm m0-m23 clb clk direct north direct to east to longlines and grm tq0-tq3 global nets feedback direct west direct south ce clr c in c out v cc /gnd ts 4 4 north 4 8 south 4 east 4 west 4 lc3 lc2 lc1 lc0 output multiplexers input multiplexers 8 4 4 4 x5724
r november 5, 1998 (version 5.2) 7-95 xc5200 series field programmable gate arrays 7 matrix through a hierarchy of different-length metal seg- ments in both the horizontal and vertical directions. a pro- grammable interconnect point (pip) establishes an electri- cal connection between two wire segments. the pip, con- sisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirec- tional) connection between two adjoining wires. a collec- tion of pips inside the general routing matrix and in the local interconnect matrix provides connectivity between various types of metal segments. a hierarchy of pips and associated routing segments combine to provide a power- ful interconnect hierarchy: ? forty bidirectional single-length segments per clb provide ten routing channels to each of the four neighboring clbs in four directions. ? sixteen bidirectional double-length segments per clb provide four routing channels to each of four other (non-neighboring) clbs in four directions. ? eight horizontal and eight vertical bidirectional longline figure 15: xc5200 interconnect structure x4963 versa- block grm single-length lines double-length lines direct connects longlines and global lines 1 six levels of routing hierarchy 1 2 3 4 5 2 3 4 versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm versa- block grm local interconnect matrix logic cell feedthrough path (contained within each logic cell) lim 5 6 clb direct connects ts lim 4 4 4 4 4 lc3 lc2 lc1 lc0 4 4 44 24 24 6 grm
r xc5200 series field programmable gate arrays 7-96 november 5, 1998 (version 5.2) segments span the width and height of the chip, respectively. two low-skew horizontal and vertical unidirectional glo- bal-line segments span each row and column of the chip, respectively. single- and double-length lines the single- and double-length bidirectional line segments make up the bulk of the routing channels. the dou- ble-length lines hop across every other clb to reduce the propagation delays in speed-critical nets. regenerating the signal strength is recommended after traversing three or four such segments. xilinx place-and-route software auto- matically connects buffers in the path of the signal as nec- essary. single- and double-length lines cannot drive onto longlines and global lines; longlines and global lines can, however, drive onto single- and double-length lines. as a general rule, longline and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. longlines longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. row and column splitter pips in the middle of the array effectively double the total number of longlines by electrically dividing them into two separated half-lines. longlines are driven by the 3-state buffers in each clb, and are driven by similar buff- ers at the periphery of the array from the versaring i/o interface. bus-oriented designs are easily implemented by using lon- glines in conjunction with the 3-state buffers in the clb and in the versaring. additionally, weak keeper cells at the periphery retain the last valid logic level on the longlines when all buffers are in 3-state mode. longlines connect to the single-length or double-length lines, or to the logic inside the clb, through the general routing matrix. the only manner in which a longline can be driven is through the four 3-state buffers; therefore, a longline-to-longline or single-line-to-longline connection through pips in the general routing matrix is not possible. again, as a general rule, long- and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. the xc5200 family has no pull-ups on the ends of the lon- glines sourced by tbufs, unlike the xc4000 series. con- sequently, wired functions (i.e., wand and worand) and wide multiplexing functions requiring pull-ups for undefined states (i.e., bus applications) must be implemented in a dif- ferent way. in the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. in the case of 3-state bus applications, the user must insure that all states of the multiplexing function are defined. this process is as simple as adding an additional tbuf to drive the bus high when the previously undefined states are activated. global lines global buffers in xilinx fpgas are special buffers that drive a dedicated routing network called global lines, as shown in figure 16 . this network is intended for high-fanout clocks or other control signals, to maximize speed and min- imize skewing while distributing the signal to many loads. the xc5200 family has a total of four global buffers (bufg symbol in the library), each with its own dedicated routing channel. two are distributed vertically and two horizontally throughout the fpga. the global lines provide direct input only to the clb clock pins. the global lines also connect to the general routing matrix to provide access from these lines to the function generators and other control signals. four clock input pads at the corners of the chip, as shown in figure 16 , provide a high-speed, low-skew clock network to each of the four global-line buffers. in addition to the ded- icated pad, the global lines can be sourced by internal logic. pips from several routing channels within the ver- saring can also be configured to drive the global-line buff- ers. details of all the programmable interconnect for a clb is shown in figure 17 . figure 16: global lines gck1 gck4 gck3 gck2 x5704
r november 5, 1998 (version 5.2) 7-97 xc5200 series field programmable gate arrays 7 . clb double global carry single long direct direct direct double single long global x9010 figure 17: detail of programmable interconnect associated with xc5200 series clb
r xc5200 series field programmable gate arrays 7-98 november 5, 1998 (version 5.2) versaring input/output interface the versaring, shown in figure 18 , is positioned between the core logic and the pad ring; it has all the routing resources of a versablock without the clb logic. the ver- saring decouples the core logic from the i/o pads. each versaring cell provides up to four pad-cell connections on one side, and connects directly to the clb ports on the other side. boundary scan the bed of nails has been the traditional method of testing electronic assemblies. this approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount technology and multi-layer boards. the ieee boundary scan standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for i/o and internal logic. this structure is easily implemented with a four-pin interface on any boundary scan-compatible ic. ieee 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. xc5200 devices support all the mandatory boundary-scan instructions specified in the ieee standard 1149.1. a test access port (tap) and registers are provided that imple- ment the extest, sample/preload, and bypass instructions. the tap can also support two usercode instructions. when the boundary scan configuration option is selected, three normal user i/o pins become dedicated inputs for these functions. another user output pin becomes the dedicated boundary scan output. boundary-scan operation is independent of individual iob configuration and package type. all iobs are treated as independently controlled bidirectional pins, including any unbonded iobs. retaining the bidirectional test capability after configuration provides flexibility for interconnect test- ing. also, internal signals can be captured during extest by connecting them to unbonded iobs, or to the unused out- puts in iobs used as unidirectional input pins. this tech- nique partially compensates for the lack of intest support. the user can serially load commands and data into these devices to control the driving of their outputs and to exam- ine their inputs. this method is an improvement over bed-of-nails testing. it avoids the need to over-drive device outputs, and it reduces the user interface to four pins. an optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in xilinx devices. the dedicated on-chip logic implementing the ieee 1149.1 functions includes a 16-state machine, an instruction regis- ter and a number of data registers. the functional details can be found in the ieee 1149.1 specification and are also discussed in the xilinx application note xapp 017: bound- ary scan in xc4000 and xc5200 series devices figure 19 on page 99 is a diagram of the xc5200-series boundary scan logic. it includes three bits of data register per iob, the ieee 1149.1 test access port controller, and the instruction register with decodes. the public boundary-scan instructions are always available prior to configuration. after configuration, the public instruc- tions and any usercode instructions are only available if specified in the design. while sample and bypass are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. in addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the fpga device, and to read back the configuration data. all of the xc4000 boundary-scan modes are supported in the xc5200 family. three additional outputs for the user- register are provided (reset, update, and shift), repre- figure 18: versaring i/o interface 8 8 grm versablock 8 versaring 2 4 8 8 4 4 4 10 2 grm versablock 8 2 2 2 2 2 2 8 10 interconnect interconnect pad pad pad pad pad pad pad pad x5705
r november 5, 1998 (version 5.2) 7-99 xc5200 series field programmable gate arrays 7 senting the decoding of the corresponding state of the boundary-scan internal state machine. d q d q d q iob iob iob iob iob iob iob iob iob iob iob iob iob m u x bypass register iob iob tdo tdi iob iob iob m u x tdo tdi iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob 1 0 1 0 1 0 1 0 1 0 1 0 1 0 dq le sd sd le dq d q d q 1 0 1 0 1 0 1 0 dq le sd sd le dq sd le dq iob d q d q 1 0 1 0 dq le sd sd le dq 1 0 data in iob.t iob.o iob.i iob.o iob.t iob.i iob.o shift/ capture clock data register dataout update extest x1523_01 instruction register instruction register bypass register figure 19: xc5200-series boundary scan logic
r xc5200 series field programmable gate arrays 7-100 november 5, 1998 (version 5.2) xc5200-series devices can also be configured through the boundary scan logic. see xapp 017 for more information. data registers the primary data register is the boundary scan register. for each iob pin in the fpga, bonded or not, it includes three bits for in, out and 3-state control. non-iob pins have appropriate partial bit population for in or out only. program , cclk and done are not included in the boundary scan register. each extest capture-dr state captures all in, out, and 3-state pins. the data register also includes the following non-pin bits: tdo.t, and tdo.o, which are always bits 0 and 1 of the data register, respectively, and bscant.upd, which is always the last bit of the data register. these three bound- ary scan bits are special-purpose xilinx test signals. the other standard data register is the single flip-flop bypass register. it synchronizes data being passed through the fpga to the next downstream boundary scan device. the fpga provides two additional data registers that can be specified using the bscan macro. the fpga provides two user pins (bscan.sel1 and bscan.sel2) which are the decodes of two user instructions, user1 and user2. for these instructions, two corresponding pins (bscan.tdo1 and bscan.tdo2) allow user scan data to be shifted out on tdo. the data register clock (bscan.drck) is available for control of test logic which the user may wish to implement with clbs. the nand of tck and run-test-idle is also provided (bscan.idle). instruction set the xc5200-series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. the instruction set is coded as shown in tab le 7 . table 7: boundary scan instructions bit sequence the bit sequence within each iob is: 3-state, out, in. the data-register cells for the tap pins tms, tck, and tdi have an or-gate that permanently disables the output buffer if boundary-scan operation is selected. conse- quently, it is impossible for the outputs in iobs used by tap inputs to conflict with tap operation. tap data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data. the primary global clock inputs (pgck1-pgck4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. however, if necessary, it is possible to drive the clock input from boundary scan. the external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clock-pad iob. if the clock-pad iobs are used for non-clock signals, the data may be overwritten normally. pull-up and pull-down resistors remain active during boundary scan. before and during configuration, all pins are pulled up. after configuration, the choice of internal pull-up or pull-down resistor must be taken into account when designing test vectors to detect open-circuit pc traces. from a cavity-up view of the chip (as shown in xde or epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in ta b l e 8 . the device-specific pinout tables for the xc5200 series include the boundary scan locations for each iob pin. table 8: boundary scan bit sequence bsdl (boundary scan description language) files for xc5200-series devices are available on the xilinx web site in the file download area. including boundary scan if boundary scan is only to be used during configuration, no special elements need be included in the schematic or hdl code. in this case, the special boundary scan pins tdi, tms, tck and tdo can be used for user functions after configuration. to indicate that boundary scan remain enabled after config- uration, include the bscan library symbol and connect pad symbols to the tdi, tms, tck and tdo pins, as shown in figure 20 . instruction i2 i1 i0 test selected tdo source i/o data source 0 0 0 extest dr dr 0 0 1 sample/pr eload dr pin/logic 0 1 0 user 1 bscan. tdo1 user logic 0 1 1 user 2 bscan. tdo2 user logic 1 0 0 readback readback data pin/logic 1 0 1 configure dout disabled 1 1 0 reserved 1 1 1 bypass bypass register bit position i/o pad location bit 0 (tdo) top-edge i/o pads (right to left) bit 1 ... ... left-edge i/o pads (top to bottom) ... bottom-edge i/o pads (left to right) ... right-edge i/o pads (bottom to top) bit n (tdi) bscant.upd
r november 5, 1998 (version 5.2) 7-101 xc5200 series field programmable gate arrays 7 even if the boundary scan symbol is used in a schematic, the input pins tms, tck, and tdi can still be used as inputs to be routed to internal logic. care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. the simplest way to prevent this is to keep tms high, and then apply whatever signal is desired to tdi and tck. avoiding inadvertent boundary scan if tms or tck is used as user i/o, care must be taken to ensure that at least one of these pins is held constant dur- ing configuration. in some applications, a situation may occur where tms or tck is driven during configuration. this may cause the device to go into boundary scan mode and disrupt the configuration process. to prevent activation of boundary scan during configura- tion, do either of the following: ? tms: tie high to put the test access port controller in a benign reset state ? tck: tie high or lowdo not toggle this clock input. for more information regarding boundary scan, refer to the xilinx application note xapp 017, boundary scan in xc4000 and xc5200 devices . power distribution power for the fpga is distributed through a grid to achieve high noise immunity and isolation between logic and i/o. inside the fpga, a dedicated vcc and ground ring sur- rounding the logic array provides power to the i/o drivers, as shown in figure 21 . an independent matrix of vcc and ground lines supplies the interior logic of the device. this power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. typically, a 0.1 m f capacitor connected near the vcc and ground pins of the package will provide adequate decou- pling. output buffers capable of driving/sinking the specified 8 ma loads under specified worst-case conditions may be capa- ble of driving/sinking up to 10 times as much current under best case conditions. noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. it may also be beneficial to locate heavily loaded output buffers near the ground pads. the i/o block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical. pin descriptions there are three types of pins in the xc5200-series devices: ? permanently dedicated pins ? user i/o pins that can have special functions ? unrestricted user-programmable i/o pins. before and during configuration, all outputs not used for the configuration process are 3-stated and pulled high with a 20 k w - 100 k w pull-up resistor. after configuration, if an iob is unused it is configured as an input with a 20 k w - 100 k w pull-up resistor. device pins for xc5200-series devices are described in tab le 9 . pin functions during configuration for each of the seven configuration modes are summarized in pin func- tdi tms tck tdo1 tdo2 tdo drck idle sel1 sel2 reset update shift bscan to user logic ibuf optional from user logic to user logic x9000 figure 20: boundary scan schematic example gnd ground and vcc ring for i/o drivers vcc gnd vcc logic power grid x5422 figure 21: xc5200-series power distribution
r xc5200 series field programmable gate arrays 7-102 november 5, 1998 (version 5.2) tions during configuration on page 124 , in the configura- tion timing section. table 9: pin descriptions pin name i/o during config. i/o after config. pin description permanently dedicated pins vcc i i five or more (depending on package) connections to the nominal +5 v supply voltage. all must be connected, and each must be decoupled with a 0.01 - 0.1 m f capacitor to ground. gnd i i four or more (depending on package type) connections to ground. all must be con- nected. cclk i or o i during configuration, configuration clock (cclk) is an output in master modes or asyn- chronous peripheral mode, but is an input in slave mode, synchronous peripheral mode, and express mode. after configuration, cclk has a weak pull-up resistor and can be selected as the readback clock. there is no cclk high time restriction on xc5200-series devices, except during readback. see violating the maximum high and low time specification for the readback clock on page 113 for an explanation of this exception. done i/o o done is a bidirectional signal with an optional internal pull-up resistor. as an output, it indicates the completion of the configuration process. as an input, a low level on done can be configured to delay the global logic initialization and the enabling of out- puts. the exact timing, the clock source for the low-to-high transition, and the optional pull-up resistor are selected as options in the program that creates the configuration bit- stream. the resistor is included by default. program ii program is an active low input that forces the fpga to clear its configuration mem- ory. it is used to initiate a configuration cycle. when program goes high, the fpga executes a complete clear cycle, before it goes into a wait state and releases init . the program pin has an optional weak pull-up after configuration. user i/o pins that can have special functions rdy/busy oi/o during peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the fpga. the same status is also available on d7 in asyn- chronous peripheral mode, if a read operation is performed when the device is selected. after configuration, rdy/busy is a user-programmable i/o pin. rdy/busy is pulled high with a high-impedance pull-up prior to init going high. rclk oi/o during master parallel configuration, each change on the a0-a17 outputs is preceded by a rising edge on rclk , a redundant output signal. rclk is useful for clocked proms. it is rarely used during configuration. after configuration, rclk is a user-pro- grammable i/o pin. m0, m1, m2 i i/o as mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. after configuration, m0, m1, and m2 become us- er-programmable i/o. during configuration, these pins have weak pull-up resistors. for the most popular con- figuration mode, slave serial, the mode pins can thus be left unconnected. a pull-down resistor value of 3.3 k w is recommended for other modes. tdo o o if boundary scan is used, this pin is the test data output. if boundary scan is not used, this pin is a 3-state output, after configuration is completed. this pin can be user output only when called out by special schematic definitions. to use this pin, place the library component tdo instead of the usual pad symbol. an out- put buffer must still be used.
r november 5, 1998 (version 5.2) 7-103 xc5200 series field programmable gate arrays 7 tdi, tck, tms i i/o or i (jtag) if boundary scan is used, these pins are test data in, test clock, and test mode select inputs respectively. they come directly from the pads, bypassing the iobs. these pins can also be used as inputs to the clb logic after configuration is completed. if the bscan symbol is not placed in the design, all boundary scan functions are inhib- ited once configuration is completed, and these pins become user-programmable i/o. in this case, they must be called out by special schematic definitions. to use these pins, place the library components tdi, tck, and tms instead of the usual pad symbols. in- put or output buffers must still be used. hdc o i/o high during configuration (hdc) is driven high until the i/o go active. it is available as a control output indicating that configuration is not yet completed. after configuration, hdc is a user-programmable i/o pin. ldc oi/o low during configuration (ldc ) is driven low until the i/o go active. it is available as a control output indicating that configuration is not yet completed. after configuration, ldc is a user-programmable i/o pin. init i/o i/o before and during configuration, init is a bidirectional signal. a 1 k w - 10 k w external pull-up resistor is recommended. as an active-low open-drain output, init is held low during the power stabilization and internal clearing of the configuration memory. as an active-low input, it can be used to hold the fpga in the internal wait state before the start of configuration. master mode devices stay in a wait state an additional 50 to 250 m s after init has gone high. during configuration, a low on this output indicates that a configuration data error has occurred. after the i/o go active, init is a user-programmable i/o pin. gck1 - gck4 weak pull-up i or i/o four global inputs each drive a dedicated internal global net with short delay and min- imal skew. these internal global nets can also be driven from internal logic. if not used to drive a global net, any of these pins is a user-programmable i/o pin. the gck1-gck4 pins provide the shortest path to the four global buffers. any input pad symbol connected directly to the input of a bufg symbol is automatically placed on one of these pins. cs0 , cs1, ws , rs ii/o these four inputs are used in asynchronous peripheral mode. the chip is selected when cs0 is low and cs1 is high. while the chip is selected, a low on write strobe (ws ) loads the data present on the d0 - d7 inputs into the internal data buffer. a low on read strobe (rs ) changes d7 into a status output high if ready, low if busy and drives d0 - d6 high. in express mode, cs1 is used as a serial-enable signal for daisy-chaining. ws and rs should be mutually exclusive, but if both are low simultaneously, the write strobe overrides. after configuration, these are user-programmable i/o pins. a0 - a17 o i/o during master parallel configuration, these 18 output pins address the configuration eprom. after configuration, they are user-programmable i/o pins. d0 - d7 i i/o during master parallel, peripheral, and express configuration, these eight input pins re- ceive configuration data. after configuration, they are user-programmable i/o pins. din i i/o during slave serial or master serial configuration, din is the serial configuration data input receiving data on the rising edge of cclk. during parallel configuration, din is the d0 input. after configuration, din is a user-programmable i/o pin. dout o i/o during configuration in any mode but express mode, dout is the serial configuration data output that can drive the din of daisy-chained slave fpgas. dout data changes on the falling edge of cclk. in express mode, dout is the status output that can drive the cs1 of daisy-chained fpgas, to enable and disable downstream devices. after configuration, dout is a user-programmable i/o pin. table 9: pin descriptions (continued) pin name i/o during config. i/o after config. pin description
r xc5200 series field programmable gate arrays 7-104 november 5, 1998 (version 5.2) configuration configuration is the process of loading design-specific pro- gramming data into one or more fpgas to define the func- tional operation of the internal blocks and their interconnections. this is somewhat like loading the com- mand registers of a programmable peripheral chip. xc5200-series devices use several hundred bits of config- uration data per clb and its associated interconnects. each configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multi- plexer input, or an interconnect pass transistor. the devel- opment system translates the design into a netlist file. it automatically partitions, places and routes the logic and generates the configuration data in prom format. special purpose pins three configuration mode pins (m2, m1, m0) are sampled prior to configuration to determine the configuration mode. after configuration, these pins can be used as auxiliary i/o connections. the development system does not use these resources unless they are explicitly specified in the design entry. this is done by placing a special pad symbol called md2, md1, or md0 instead of the input or output pad sym- bol. in xc5200-series devices, the mode pins have weak pull-up resistors during configuration. with all three mode pins high, slave serial mode is selected, which is the most popular configuration mode. therefore, for the most com- mon configuration mode, the mode pins can be left uncon- nected. (note, however, that the internal pull-up resistor value can be as high as 100 k w .) after configuration, these pins can individually have weak pull-up or pull-down resis- tors, as specified in the design. a pull-down resistor value of 3.3k w is recommended. these pins are located in the lower left chip corner and are near the readback nets. this location allows convenient routing if compatibility with the xc2000 and xc3000 family conventions of m0/rt, m1/rd is desired. configuration modes xc5200 devices have seven configuration modes. these modes are selected by a 3-bit input code applied to the m2, m1, and m0 inputs. there are three self-loading master modes, two peripheral modes, and a serial slave mode, note :*peripheral synchronous can be considered byte-wide slave parallel which is used primarily for daisy-chained devices. the sev- enth mode, called express mode, is an additional slave mode that allows high-speed parallel configuration. the coding for mode selection is shown in ta b l e 1 0 . note that the smallest package, vq64, only supports the master serial, slave serial, and express modes.a detailed description of each configuration mode, with timing infor- mation, is included later in this data sheet. during configu- ration, some of the i/o pins are used temporarily for the configuration process. all pins used during configuration are shown in table 13 on page 124 . master modes the three master modes use an internal oscillator to gener- ate a configuration clock (cclk) for driving potential slave devices. they also generate address and timing for exter- nal prom(s) containing the configuration data. master parallel (up or down) modes generate the cclk signal and prom addresses and receive byte parallel data. the data is internally serialized into the fpga data-frame format. the up and down selection generates starting addresses at either zero or 3ffff, for compatibility with different microprocessor addressing conventions. the unrestricted user-programmable i/o pins i/o weak pull-up i/o these pins can be configured to be input and/or output after configuration is completed. before configuration is completed, these pins have an internal high-value pull-up resis- tor (20 k w - 100 k w ) that defines the logic level as high. table 9: pin descriptions (continued) pin name i/o during config. i/o after config. pin description table 10: configuration modes mode m2 m1 m0 cclk data master serial 0 0 0 output bit-serial slave serial 1 1 1 input bit-serial master parallel up 1 0 0 output byte-wide, increment from 00000 master parallel down 1 1 0 output byte-wide, decrement from 3ffff peripheral synchronous* 0 1 1 input byte-wide peripheral asynchronous 1 0 1 output byte-wide express 0 1 0 input byte-wide reserved 001
r november 5, 1998 (version 5.2) 7-105 xc5200 series field programmable gate arrays 7 master serial mode generates cclk and receives the con- figuration data in serial form from a xilinx serial-configura- tion prom. cclk speed is selectable as 1 mhz (default), 6 mhz, or 12 mhz. configuration always starts at the default slow fre- quency, then can switch to the higher frequency during the first frame. frequency tolerance is -50% to +50%. peripheral modes the two peripheral modes accept byte-wide data from a bus. a rdy/busy status is available as a handshake sig- nal. in asynchronous peripheral mode, the internal oscilla- tor generates a cclk burst signal that serializes the byte-wide data. cclk can also drive slave devices. in the synchronous mode, an externally supplied clock input to cclk serializes the data. slave serial mode in slave serial mode, the fpga receives serial configura- tion data on the rising edge of cclk and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of cclk. multiple slave devices with identical configurations can be wired with parallel din inputs. in this way, multiple devices can be configured simultaneously. serial daisy chain multiple devices with different configurations can be con- nected together in a daisy chain, and a single combined bitstream used to configure the chain of slave devices. to configure a daisy chain of devices, wire the cclk pins of all devices in parallel, as shown in figure 28 on page 114 . connect the dout of each device to the din of the next. the lead or master fpga and following slaves each passes resynchronized configuration data coming from a single source. the header data, including the length count, is passed through and is captured by each fpga when it recognizes the 0010 preamble. following the length-count data, each fpga outputs a high on dout until it has received its required number of data frames. after an fpga has received its configuration data, it passes on any additional frame start bits and configuration data on dout. when the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the fpgas begin the start-up sequence and become operational together. fpga i/o are normally released two cclk cycles after the last configura- tion bit is received. figure 25 on page 109 shows the start-up timing for an xc5200-series device. the daisy-chained bitstream is not simply a concatenation of the individual bitstreams. the prom file formatter must be used to combine the bitstreams for a daisy-chained con- figuration. multi-family daisy chain all xilinx fpgas of the xc2000, xc3000, xc4000, and xc5200 series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. there is, however, one limitation. if the chain contains xc5200-series devices, the master normally can- not be an xc2000 or xc3000 device. the reason for this rule is shown in figure 25 on page 109 . since all devices in the chain store the same length count value and generate or receive one common sequence of cclk pulses, they all recognize length-count match on the same cclk edge, as indicated on the left edge of figure 25 . the master device then generates additional cclk pulses until it reaches its finish point f. the different families generate or require different numbers of additional cclk pulses until they reach f. not reaching f means that the device does not really finish its configuration, although done may have gone high, the outputs became active, and the internal reset was released. for the xc5200-series device, not reaching f means that read- back cannot be initiated and most boundary scan instruc- tions cannot be used. the user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the finish point f is reached. timing is con- trolled using options in the bitstream generation software. xc5200 devices always have the same number of cclks in the power up delay, independent of the configuration mode, unlike the xc3000/xc4000 series devices. to guar- antee all devices in a daisy chain have finished the power-up delay, tie the init pins together, as shown in figure 27 . xc3000 master with an xc5200-series slave some designers want to use an xc3000 lead device in peripheral mode and have the i/o pins of the xc5200-series devices all available for user i/o. figure 22 provides a solution for that case. this solution requires one clb, one iob and pin, and an internal oscillator with a frequency of up to 5 mhz as a clock source. the xc3000 master device must be config- ured with late internal reset, which is the default option. one clb and one iob in the lead xc3000-family device are used to generate the additional cclk pulse required by the xc5200-series devices. when the lead device removes the internal reset signal, the 2-bit shift register responds to its clock input and generates an active low output signal for the duration of the subsequent clock period. an external connection between this output and cclk thus creates the extra cclk pulse.
r xc5200 series field programmable gate arrays 7-106 november 5, 1998 (version 5.2) express mode express mode is similar to slave serial mode, except the data is presented in parallel format, and is clocked into the target device a byte at a time rather than a bit at a time. the data is loaded in parallel into eight different columns: it is not internally serialized. eight bits of configuration data are loaded with every cclk cycle, therefore this configuration mode runs at eight times the data rate of the other six modes. in this mode the xc5200 family is capable of sup- porting a cclk frequency of 10 mhz, which is equivalent to an 80 mhz serial rate, because eight bits of configuration data are being loaded per cclk cycle. an xc5210 in the express mode, for instance, can be configured in about 2 ms. the express mode does not support crc error check- ing, but does support constant-field error checking. a length count is not used in express mode. in the express configuration mode, an external signal drives the cclk input(s). the first byte of parallel configu- ration data must be available at the d inputs of the fpga devices a short set-up time before the second rising cclk edge. subsequent data bytes are clocked in on each con- secutive rising cclk edge. see figure 38 on page 123 . bitstream generation currently generates a bitstream suffi- cient to program in all configuration modes except express. extra cclk cycles are necessary to complete the configu- ration, since in this mode data is read at a rate of eight bits per cclk cycle instead of one bit per cycle. normally the entire start-up sequence requires a number of bits that is equal to the number of cclk cycles needed. an additional five cclks (equivalent to 40 extra bits) will guarantee com- pletion of configuration, regardless of the start-up options chosen. multiple slave devices with identical configurations can be wired with parallel d0-d7 inputs. in this way, multiple devices can be configured simultaneously. pseudo daisy chain multiple devices with different configurations can be con- nected together in a pseudo daisy chain, provided that all of the devices are in express mode. a single combined bit- stream is used to configure the chain of express mode devices, but the input data bus must drive d0-d7 of each device. tie high the cs1 pin of the first device to be config- ured, or leave it floating in the xc5200 since it has an inter- nal pull-up. connect the dout pin of each fpga to the cs1 pin of the next device in the chain. the d0-d7 inputs are wired to each device in parallel. the done pins are wired together, with one or more internal done pull-ups activated. alternatively, a 4.7 k w external resistor can be used, if desired. (see figure 37 on page 122 .) cclk pins are tied together. the requirement that all done pins in a daisy chain be wired together applies only to express mode, and only if all devices in the chain are to become active simultaneously. all devices in express mode are synchronized to the done pin. user i/o for each device become active after the done pin for that device goes high. (the exact timing is determined by options to the bitstream generation soft- ware.) since the done pin is open-drain and does not drive a high value, tying the done pins of all devices together prevents all devices in the chain from going high until the last device in the chain has completed its configu- ration cycle. the status pin dout is pulled low two internal-oscillator cycles (nominally 1 mhz) after init is recognized as high, and remains low until the devices configuration memory is full. then dout is pulled high to signal the next device in the chain to accept the configuration data on the d7-d0 bus. all devices receive and recognize the six bytes of pre- amble and length count, irrespective of the level on cs1; but subsequent frame data is accepted only when cs1 is high and the devices configuration memory is not already full. setting cclk frequency for master modes, cclk can be generated in one of three frequencies. in the default slow mode, the frequency is nominally 1 mhz. in fast cclk mode, the frequency is nominally 12 mhz. in medium cclk mode, the frequency is nominally 6 mhz. the frequency range is -50% to +50%. the frequency is selected by an option when running the bitstream generation software. if an xc5200-series master is driving an xc3000- or xc2000-family slave, slow cclk mode must be used. slow mode is the default. output connected to cclk oe/t 0 1 1 0 0 . . 0 0 1 1 1 . . reset x5223 etc active low output active high output figure 22: cclk generation for xc3000 master driving an xc5200-series slave table 11: xc5200 bitstream format data type value occurrences fill byte 11111111 once per bit- stream preamble 11110010 length counter count(23:0) fill byte 11111111
r november 5, 1998 (version 5.2) 7-107 xc5200 series field programmable gate arrays 7 data stream format the data stream (bitstream) format is identical for all con- figuration modes, with the exception of express mode. in express mode, the device becomes active when done goes high, therefore no length count is required. addition- ally, crc error checking is not supported in express mode. the data stream formats are shown in ta b l e 11 . express mode data is shown with d0 at the left and d7 at the right. for all other modes, bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bit in each byte assigned to d0. the configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones (or 24 fill bits, in express mode). this header is followed by the actual configuration data in frames. the length and number of frames depends on the device type (see tab le 12 ). each frame begins with a start field and ends with an error check. in all modes except express mode, a postamble code is required to sig- nal the end of data for a single device. in all cases, addi- tional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. long daisy chains require additional startup bytes to shift the last data through the chain. all startup bytes are dont-cares; these bytes are not included in bitstreams cre- ated by the xilinx software. in express mode, only non-crc error checking is sup- ported. in all other modes, a selection of crc or non-crc error checking is allowed by the bitstream generation soft- ware. the non-crc error checking tests for a designated end-of-frame field for each frame. for crc error checking, the software calculates a running crc and inserts a unique four-bit partial check at the end of each frame. the 11-bit crc check of the last frame of an fpga includes the last seven data bits. detection of an error results in the suspension of data load- ing and the pulling down of the init pin. in master modes, cclk and address signals continue to operate externally. the user must detect init and initialize a new configuration by pulsing the program pin low or cycling vcc. cyclic redundancy check (crc) for configuration and readback the cyclic redundancy check is a method of error detec- tion in data transmission applications. generally, the trans- mitting system performs a calculation on the serial bitstream. the result of this calculation is tagged onto the data stream as additional check bits. the receiving system performs an identical calculation on the bitstream and com- pares the result with the received checksum. each data frame of the configuration bitstream has four error bits at the end, as shown in tab le 11 . if a frame data error is detected during the loading of the fpga, the con- figuration process with a potentially corrupted bitstream is terminated. the fpga pulls the init pin low and goes into a wait state. during readback, 11 bits of the 16-bit checksum are added to the end of the readback data stream. the checksum is computed using the crc-16 ccitt polynomial, as shown in figure 23 . the checksum consists of the 11 most signifi- cant bits of the 16-bit code. a change in the checksum indi- cates a change in the readback bitstream. a comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. clb out- puts should not be included (read capture option not used). statistically, one error out of 2048 might go undetec- ted. start byte 11111110 once per data frame data frame * data(n-1:0) cyclic redundancy check or constant field check crc(3:0) or 0110 fill nibble 1111 extend write cycle ffffff postamble 11111110 once per de- vice fill bytes (30) ffffff start-up byte ff once per bit- stream *bits per frame (n) depends on device size, as described for table 11. table 11: xc5200 bitstream format data type value occurrences table 12: internal configuration data structure device versablock array prom size (bits) xilinx serial prom needed x c 5 2 0 2 8 x 8 42 , 4 1 6 x c 1 7 65 e x c 5 2 0 4 1 0 x 1 2 70 , 7 0 4 x c 1 7 12 8 e x c 5 2 0 6 1 4 x 1 4 10 6 , 2 8 8 x c 1 7 12 8 e x c 5 2 1 0 1 8 x 1 8 16 5 , 4 8 8 x c 1 7 25 6 e x c 5 2 1 5 2 2 x 2 2 23 7 , 7 4 4 x c 1 7 25 6 e bits per frame = (34 x number of rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill bits * + 24 extended write bits = (34 x number of rows) + 100 * in the xc5202 (8 x 8), there are 8 fill bits per frame, not 4 number of frames = (12 x number of columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit = (12 x number of columns) + 16 program data = (bits per frame x number of frames) + 48 header bits + 8 postamble bits + 240 fill bits + 8 start-up bits = (bits per frame x number of frames) + 304 prom size = program data
r xc5200 series field programmable gate arrays 7-108 november 5, 1998 (version 5.2) configuration sequence there are four major steps in the xc5200-series power-up configuration sequence. ? power-on time-out ? initialization ? configuration ? start-up the full process is illustrated in figure 24 . power-on time-out an internal power-on reset circuit is triggered when power is applied. when v cc reaches the voltage at which portions of the fpga begin to operate (i.e., performs a write-and-read test of a sample pair of configuration mem- ory bits), the programmable i/o buffers are 3-stated with active high-impedance pull-up resistors. a time-out delay nominally 4 ms is initiated to allow the power-supply voltage to stabilize. for correct operation the power supply must reach v cc (min) by the end of the time-out, and must not dip below it thereafter. there is no distinction between master and slave modes with regard to the time-out delay. instead, the init line is used to ensure that all daisy-chained devices have com- pleted initialization. since xc2000 devices do not have this signal, extra care must be taken to guarantee proper oper- ation when daisy-chaining them with xc5200 devices. for proper operation with xc3000 devices, the reset signal, which is used in xc3000 to delay configuration, should be connected to init . if the time-out delay is insufficient, configuration should be delayed by holding the init pin low until the power supply has reached operating levels. this delay is applied only on power-up. it is not applied when reconfiguring an fpga by pulsing the program pin low. during all three phases power-on, initialization, and configuration done is held low; hdc, ldc , and init are active; dout is driven; and all i/o buffers are dis- abled. initialization this phase clears the configuration memory and estab- lishes the configuration mode. the configuration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 mhz). an open-drain bidirectional signal, init , is released when the configuration memory is completely cleared. the device then tests for the absence of an external active-low level on init . the mode lines are sampled two internal clock cycles later (nominally 2 m s). the master device waits an additional 32 m s to 256 m s (nominally 64-128 m s) to provide adequate time for all of the slave devices to recognize the release of init as well. then the master device enters the configuration phase. 0 x2 2 3456789101112 13 14 1 x15 x16 15 serial data in 1 0 151413121110 9 8 7 65 1 1 1 1 crc ?checksum last data frame start bit x1789 polynomial: x16 + x15 + x2 + 1 readback data stream figure 23: circuit for generating crc-16 figure 24: configuration sequence init high? if master sample mode lines load one configuration data frame frame error pass configuration data to dout v cc 3v no yes yes no no yes operational start-up sequence no yes ~1.3 m s per frame master cclk goes active after 50 to 250 s f pull init low and stop x9017 extest* sample/preload* bypass configure* (*only when program = high) sample/preload bypass extest sample preload bypass user 1 user 2 configure readback if boundary scan is selected config- uration memory full cclk count equals length count completely clear configuration memory ldc output = l, hdc output = h boundary scan instructions available: i/o active generate one time-out pulse of 4 ms program = low no yes yes
r november 5, 1998 (version 5.2) 7-109 xc5200 series field programmable gate arrays 7 xc4000e/ex xc5200/ uclk_sync xc4000e/ex xc5200/ uclk_nosync xc4000e/ex xc5200/ cclk_sync xc4000e/ex xc5200/ cclk_nosync xc3000 xc2000 cclk gsr active uclk period done in done in di di+1 di+2 di di+1 di+2 u2 u3 u4 u2 u3 u4 u2 u3 u4 c1 synchronization uncertainty di di+1 di di+1 done i/o gsr active done i/o gsr active done c1 c2 c1 u2 c3 c4 c2 c3 c4 c2 c3 c4 i/o gsr active done i/o done global reset i/o done global reset i/o f = finished, no more configuration clocks needed daisy-chain lead device must have latest f heavy lines describe default timing cclk period length count match f f f f f f x6700 c1, c2 or c3 figure 25: start-up timing
r xc5200 series field programmable gate arrays 7-110 november 5, 1998 (version 5.2) configuration the length counter begins counting immediately upon entry into the configuration state. in slave-mode operation it is important to wait at least two cycles of the internal 1-mhz clock oscillator after init is recognized before toggling cclk and feeding the serial bitstream. configuration will not begin until the internal configuration logic reset is released, which happens two cycles after init goes high. a master devices configuration is delayed from 32 to 256 m s to ensure proper operation with any slave devices driven by the master device. the 0010 preamble code, included for all modes except express mode, indicates that the following 24 bits repre- sent the length count. the length count is the total number of configuration clocks needed to load the complete config- uration data. (four additional configuration clocks are required to complete the configuration process, as dis- cussed below.) after the preamble and the length count have been passed through to all devices in the daisy chain, dout is held high to prevent frame start bits from reaching any daisy-chained devices. in express mode, the length count bits are ignored, and dout is held low, to disable the next device in the pseudo daisy chain. a specific configuration bit, early in the first frame of a mas- ter device, controls the configuration-clock rate and can increase it by a factor of eight. therefore, if a fast configu- ration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. each frame has a start field followed by the frame-configu- ration data bits and a frame error field. if a frame data error is detected, the fpga halts loading, and signals the error by pulling the open-drain init pin low. after all configura- tion frames have been loaded into an fpga, dout again follows the input data so that the remaining data is passed on to the next device. in express mode, when the first device is fully programmed, dout goes high to enable the next device in the chain. delaying configuration after power-up to delay master mode configuration after power-up, pull the bidirectional init pin low, using an open-collector (open-drain) driver. (see figure 12 .) using an open-collector or open-drain driver to hold init low before the beginning of master mode configuration causes the fpga to wait after completing the configuration memory clear operation. when init is no longer held low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configura- tion process. a master device waits up to an additional 250 m s to make sure that any slaves in the optional daisy chain have seen that init is high. start-up start-up is the transition from the configuration process to the intended user operation. this transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with i/o pins active in the user-system. start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the configu- ration signals, and that the internal flip-flops are released from the global reset at the right time. figure 25 describes start-up timing for the three xilinx fam- ilies in detail. express mode configuration always uses either cclk_sync or uclk_sync timing, the other con- figuration modes can use any of the four timing sequences. to access the internal start-up signals, place the startup library symbol. start-up timing different fpga families have different start-up sequences. the xc2000 family goes through a fixed sequence. done goes high and the internal global reset is de-activated one cclk period after the i/o become active. the xc3000a family offers some flexibility. done can be programmed to go high one cclk period before or after the i/o become active. independent of done, the internal global reset is de-activated one cclk period before or after the i/o become active. the xc4000/xc5200 series offers additional flexibility. the three events done going high, the internal reset being de-activated, and the user i/o going active can all occur in any arbitrary sequence. each of them can occur one cclk period before or after, or simultaneous with, any of the others. this relative timing is selected by means of software options in the bitstream generation software. the default option, and the most practical one, is for done to go high first, disconnecting the configuration data source and avoiding any contention when the i/os become active one clock later. reset is then released another clock period later to make sure that user-operation starts from stable internal conditions. this is the most common sequence, shown with heavy lines in figure 25 , but the designer can modify it to meet particular requirements. normally, the start-up sequence is controlled by the internal device oscillator output (cclk), which is asynchronous to the system clock. xc4000/xc5200 series offers another start-up clocking option, uclk_nosync. the three events described above need not be triggered by cclk. they can, as a con- figuration option, be triggered by a user clock. this means that the device can wake up in synchronism with the user system.
r november 5, 1998 (version 5.2) 7-111 xc5200 series field programmable gate arrays 7 when the uclk_sync option is enabled, the user can externally hold the open-drain done output low, and thus stall all further progress in the start-up sequence until done is released and has gone high. this option can be used to force synchronization of several fpgas to a com- mon user clock, or to guarantee that all devices are suc- cessfully configured before any i/os go active. if either of these two options is selected, and no user clock is specified in the design or attached to the device, the chip could reach a point where the configuration of the device is complete and the done pin is asserted, but the outputs do not become active. the solution is either to recreate the bitstream specifying the start-up clock as cclk, or to sup- ply the appropriate user clock. start-up sequence the start-up sequence begins when the configuration memory is full, and the total number of configuration clocks received since init went high equals the loaded value of the length count. the next rising clock edge sets a flip-flop q0, shown in figure 26 . q0 is the leading bit of a 5-bit shift register. the outputs of this register can be programmed to control three events. ? the release of the open-drain done output ? the change of configuration-related pins to the user function, activating all iobs. ? the termination of the global set/reset initialization of all clb and iob storage elements. the done pin can also be wire-anded with done pins of other fpgas or with other external signals, and can then be used as input to bit q3 of the start-up register. this is called start-up timing synchronous to done in and is selected by either cclk_sync or uclk_sync. when done is not used as an input, the operation is called start-up timing not synchronous to done in, and is selected by either cclk_nosync or uclk_nosync. as a configuration option, the start-up control register beyond q0 can be clocked either by subsequent cclk pulses or from an on-chip user net called startup.clk. these signals can be accessed by placing the startup library symbol. start-up from cclk if cclk is used to drive the start-up, q0 through q3 pro- vide the timing. heavy lines in figure 25 show the default timing, which is compatible with xc2000 and xc3000 devices using early done and late reset. the thin lines indicate all other possible timing options. start-up from a user clock (startup.clk) when, instead of cclk, a user-supplied start-up clock is selected, q1 is used to bridge the unknown phase relation- ship between cclk and the user clock. this arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence. done goes high to signal end of configuration in all configuration modes except express mode, xc5200-series devices read the expected length count from the bitstream and store it in an internal register. the length count varies according to the number of devices and the composition of the daisy chain. each device also counts the number of cclks during configuration. two conditions have to be met in order for the done pin to go high: ? the chip's internal memory must be full, and ? the configuration length count must be met, exactly . this is important because the counter that determines when the length count is met begins with the very first cclk, not the first one after the preamble. therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the first cclk, the internal counter that holds the number of cclks will be one ahead of the actual number of data bits read. at the end of configuration, the configuration memory will be full, but the number of bits in the internal counter will not match the expected length count. as a consequence, a master mode device will continue to send out cclks until the internal counter turns over to zero, and then reaches the correct length count a second time. this will take several seconds [2 24 * cclk period] which is sometimes interpreted as the device not config- uring at all. if it is not possible to have the data ready at the time of the first cclk, the problem can be avoided by increasing the number in the length count by the appropriate value. in express mode, there is no length count. the done pin for each device goes high when the device has received its quota of configuration data. wiring the done pins of sev- eral devices together delays start-up of all devices until all are fully configured. note that done is an open-drain output and does not go high unless an internal pull-up is activated or an external pull-up is attached. the internal pull-up is activated as the default by the bitstream generation software. release of user i/o after done goes high by default, the user i/o are released one cclk cycle after the done pin goes high. if cclk is not clocked after done goes high, the outputs remain in their initial state 3-stated, with a 20 k w - 100 k w pull-up. the delay from
r xc5200 series field programmable gate arrays 7-112 november 5, 1998 (version 5.2) done high to active user i/o is controlled by an option to the bitstream generation software. release of global reset after done goes high by default, global reset (gr) is released two cclk cycles after the done pin goes high. if cclk is not clocked twice after done goes high, all flip-flops are held in their initial reset state. the delay from done high to gr inactive is controlled by an option to the bitstream generation soft- ware. configuration complete after done goes high three full cclk cycles are required after the done pin goes high, as shown in figure 25 on page 109 . if cclk is not clocked three times after done goes high, readback cannot be initiated and most boundary scan instructions cannot be used. configuration through the boundary scan pins xc5200-series devices can be configured through the boundary scan pins. for detailed information, refer to the xilinx application note xapp017, boundary scan in xc4000 and xc5200 devices . readback the user can read back the content of configuration mem- ory and the level of certain internal nodes without interfer- ing with the normal operation of the device. readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in clbs. done * * * * ** qs r 1 0 0 1 1 0 1 0 1 0 0 1 gr enable gr invert startup.gr startup.gts gts invert gts enable controlled by startup symbol in the user schematic (see libraries guide) global reset of all clb flip-flops/latches iobs operational per configuration global 3-state of all iobs q2 q3 q1/q4 done in startup q0 q1 q2 q3 q4 m m " finished " enables boundary scan, readback and controls the oscillator k sq k dq k dq k dq k dq full length count clear memory cclk startup.clk user net configuration bit options selected by user x9002 figure 26: start-up logic
r november 5, 1998 (version 5.2) 7-113 xc5200 series field programmable gate arrays 7 note that in xc5200-series devices, configuration data is not inverted with respect to configuration as it is in xc2000 and xc3000 families. readback of express mode bitstreams results in data that does not resemble the original bitstream, because the bit- stream format differs from other modes. xc5200-series readback does not use any dedicated pins, but uses four internal nets (rdbk.trig, rdbk.data, rdbk.rip and rdbk.clk) that can be routed to any iob. to access the internal readback sig- nals, place the readback library symbol and attach the appropriate pad symbols, as shown in figure 27 . after readback has been initiated by a low-to-high transi- tion on rdbk.trig, the rdbk.rip (read in progress) output goes high on the next rising edge of rdbk.clk. subsequent rising edges of this clock shift out readback data on the rdbk.data net. readback data does not include the preamble, but starts with five dummy bits (all high) followed by the start bit (low) of the first frame. the first two data bits of the first frame are always high. each frame ends with four error check bits. they are read back as high. the last seven bits of the last frame are also read back as high. an additional start bit (low) and an 11-bit cyclic redundancy check (crc) signature follow, before rdbk.rip returns low. readback options readback options are: read capture, read abort, and clock select. they are set with the bitstream generation software. read capture when the read capture option is selected, the readback data stream includes sampled values of clb and iob sig- nals. the rising edge of rdbk.trig latches the inverted values of the clb outputs and the iob output and input sig- nals. note that while the bits describing configuration (interconnect and function generators) are not inverted, the clb and iob output signals are inverted. when the read capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. the readback signals are located in the lower-left corner of the device. read abort when the read abort option is selected, a high-to-low transition on rdbk.trig terminates the readback opera- tion and prepares the logic to accept another trigger. after an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. the status of readback is indi- cated by the output control net rdbk.rip. rdbk.rip is high whenever a readback is in progress. clock select cclk is the default clock. however, the user can insert another clock on rdbk.clk. readback control and data are clocked on rising edges of rdbk.clk. if readback must be inhibited for security reasons, the readback control nets are simply not connected. violating the maximum high and low time specification for the readback clock the readback clock has a maximum high and low time specification. in some cases, this specification cannot be met. for example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. this necessitates stopping the clock, and thus violating the specification. the specification is mandatory only on clocking data at the end of a frame prior to the next start bit. the transfer mech- anism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the follow- ing frame. this loading process is dynamic, and is the source of the maximum high and low time requirements. therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. at other times, the frame data is already in the register and the register is not dynamic. thus, it can be shifted out just like a regular shift register. the user must precisely calculate the location of the read- back data relative to the frame. the system must keep track of the position within a data frame, and disable inter- rupts before frame boundaries. frame lengths and data for- mats are listed in ta b l e 11 and table 12 . readback with the xchecker cable the xchecker universal download/readback cable and logic probe uses the readback feature for bitstream verifi- cation. it can also display selected internal signals on the pc or workstation screen, functioning as a low-cost in-cir- cuit emulator. readback data rip trig clk read_data obuf md1 md0 read_trigger ibuf x1786 if unconnected, default is cclk figure 27: readback schematic example
r xc5200 series field programmable gate arrays 7-114 november 5, 1998 (version 5.2) configuration timing the seven configuration modes are discussed in detail in this section. timing specifications are included. slave serial mode in slave serial mode, an external signal drives the cclk input of the fpga. the serial configuration bitstream must be available at the din input of the lead fpga a short setup time before each rising cclk edge. the lead fpga then presents the preamble dataand all data that overflows the lead deviceon its dout pin. there is an internal delay of 0.5 cclk periods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the sub- sequent rising cclk edge. figure 28 shows a full master/slave system. an xc5200-series device in slave serial mode should be con- nected as shown in the third device from the left. slave serial mode is selected by a <111> on the mode pins (m2, m1, m0). slave serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resis- tors during configuration. note: configuration must be delayed until the init pins of all daisy-chained fpgas are high. figure 29: slave serial mode programming switching characteristics xc5200 master serial spartan, xc4000e/ex, xc5200 slave xc3100a slave xc1700e program note: m2, m1, m0 can be shorted to ground if not used as i/o note: m2, m1, m0 can be shorted to vcc if not used as i/o m2 m0 m1 dout cclk clk vcc +5 v data ce ceo vpp reset/oe done din ldc init init done program program d/p init reset cclk din cclk dindout dout m2 m0 m1 m1 pwrdn m0 m2 (low reset option used) 4.7 k 3 . 3 k 3 . 3 k 3. 3 k 3 . 3 k 3 . 3 k 3 . 3 k vcc x9003_01 n/c n/c figure 28: master/slave serial mode circuit diagram 4 t cch bit n bit n + 1 bit nbit n - 1 3 t cco 5 t ccl 2 t ccd 1 t dcc din cclk dout (output) x5379 description symbol min max units cclk din setup 1 t dcc 20 ns din hold 2 t ccd 0ns din to dout 3 t cco 30 ns high time 4 t cch 45 ns low time 5 t ccl 45 ns frequency f cc 10 mhz
r november 5, 1998 (version 5.2) 7-115 xc5200 series field programmable gate arrays 7 master serial mode in master serial mode, the cclk output of the lead fpga drives a xilinx serial prom that feeds the fpga din input. each rising edge of the cclk output increments the serial prom internal address counter. the next data bit is put on the sprom data output, connected to the fpga din pin. the lead fpga accepts this data on the subsequent rising cclk edge. the lead fpga then presents the preamble dataand all data that overflows the lead deviceon its dout pin. there is an internal pipeline delay of 1.5 cclk periods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. in the bitstream generation software, the user can specify fast configrate, which, starting several bits into the first frame, increases the cclk frequency by a factor of twelve. the value increases from a nominal 1 mhz, to a nominal 12 mhz. be sure that the serial prom and slaves are fast enough to support this data rate. the medium configrate option changes the frequency to a nominal 6 mhz. xc2000, xc3000/a, and xc3100a devices do not support the fast or medium configrate options. the sprom ce input can be driven from either ldc or done. using ldc avoids potential contention on the din pin, if this pin is configured as user-i/o, but ldc is then restricted to be a permanently high user output after con- figuration. using done can also avoid contention on din, provided the done before i/o enable option is invoked. figure 28 on page 114 shows a full master/slave system. the leftmost device is in master serial mode. master serial mode is selected by a <000> on the mode pins (m2, m1, m0). notes: 1. at power-up, vcc must rise from 2.0 v to vcc min in less than 25 ms, otherwise delay configuration by pulling program low until vcc is valid. 2. master serial mode timing is based on testing in slave mode. figure 30: master serial mode programming switching characteristics in the two master parallel modes, the lead fpga directly addresses an industry-standard byte-wide eprom, and accepts eight data bits just before incrementing or decre- menting the address outputs. the eight data bits are serialized in the lead fpga, which then presents the preamble dataand all data that over- flows the lead deviceon its dout pin. there is an inter- nal delay of 1.5 cclk periods, after the rising cclk edge that accepts a byte of data (and also changes the eprom address) until the falling cclk edge that makes the lsb (d0) of this byte appear at dout. this means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. the prom address pins can be incremented or decre- mented, depending on the mode pin settings. this option allows the fpga to share the prom with a wide variety of microprocessors and microcontrollers. some processors must boot from the bottom of memory (all zeros) while oth- ers must boot from the top. the fpga is flexible and can load its configuration bitstream from either end of the mem- ory. master parallel up mode is selected by a <100> on the mode pins (m2, m1, m0). the eprom addresses start at 00000 and increment. master parallel down mode is selected by a <110> on the mode pins. the eprom addresses start at 3ffff and decrement. serial data in cclk (output) serial dout (output) 1 t dsck 2 t ckds n n + 1 n + 2 n ?3 n ?2 n ?1 n x3223 description symbol min max units cclk din setup 1 t dsck 20 ns din hold 2 t ckds 0ns
r xc5200 series field programmable gate arrays 7-116 november 5, 1998 (version 5.2) m0 m1 dout vcc m2 program d7 d6 d5 d4 d3 d2 d1 d0 program cclk din m0 m1 m2 dout program eprom (8k x 8) (or larger) a10 a11 a12 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 done d6 d5 d4 d3 d2 d1 d0 n/c n/c ce oe xc5200/ xc4000e/ex/ spartan slave 8 data bus cclk a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 init init . . . . . . . . . user control of higher order prom address bits can be used to select between alternative configurations done to din of optional daisy-chained fpgas a16 . . . a17 . . . high or low x9004_01 to cclk of optional daisy-chained fpgas 3.3 k 4.7k note:m0 can be shorted to ground if not used as i/o. xc5200 master parallel figure 31: master parallel mode circuit diagram
r november 5, 1998 (version 5.2) 7-117 xc5200 series field programmable gate arrays 7 . note: 1. at power-up, v cc must rise from 2.0 v to v cc min in less then 25 ms, otherwise delay configuration by pulling program low until v cc is valid. 2. the first data byte is loaded and cclk starts at the end of the first rclk active cycle (rising edge). this timing diagram shows that the eprom requirements are extremely relaxed. eprom access time can be longer than 500 ns. eprom data output has no hold-time requirements. figure 32: master parallel mode programming switching characteristics address for byte n byte 2 t drc address for byte n + 1 d7 d6 a0-a17 (output) d0-d7 rclk (output) cclk (output) dout (output) 1 t rac 7 cclks cclk 3 t rcd b y te n - 1 x6078 description symbol min max units cclk delay to address valid 1 t rac 0 200 ns data setup time 2 t drc 60 ns data hold time 3 t rcd 0ns
r xc5200 series field programmable gate arrays 7-118 november 5, 1998 (version 5.2) synchronous peripheral mode synchronous peripheral mode can also be considered slave parallel mode. an external signal drives the cclk input(s) of the fpga(s). the first byte of parallel configura- tion data must be available at the data inputs of the lead fpga a short setup time before the rising cclk edge. subsequent data bytes are clocked in on every eighth con- secutive rising cclk edge. the same cclk edge that accepts data, also causes the rdy/busy output to go high for one cclk period. the pin name is a misnomer. in synchronous peripheral mode it is really an acknowledge signal. synchronous operation does not require this response, but it is a meaningful signal for test purposes. note that rdy/busy is pulled high with a high-impedance pullup prior to init going high. the lead fpga serializes the data and presents the pre- amble data (and all data that overflows the lead device) on its dout pin. there is an internal delay of 1.5 cclk peri- ods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. in order to complete the serial shift operation, 10 additional cclk rising edges are required after the last data byte has been loaded, plus one more cclk cycle for each daisy-chained device. synchronous peripheral mode is selected by a <011> on the mode pins (m2, m1, m0). x9005 control signals data bus program dout m0 m1 m2 d 0-7 init done program 4.7 k w 3.3 k w 3.3 k w rdy/busy v cc optional daisy-chained fpgas note: m2 can be shorted to ground if not used as i/o cclk clock program dout xc5200e/ex slave m0 m1 n/c 8 m2 din init done cclk n/c xc5200 synchro- nous peripheral figure 33: synchronous peripheral mode circuit diagram
r november 5, 1998 (version 5.2) 7-119 xc5200 series field programmable gate arrays 7 notes: 1. peripheral synchronous mode can be considered slave parallel mode. an external cclk provides timing, clocking in the first data byte on the second rising edge of cclk after init goes high. subsequent data bytes are clocked in on every eighth consecutive rising edge of cclk. 2. the rdy/busy line goes high for one cclk period after data has been clocked in, although synchronous operation does not require such a response. 3. the pin name rdy/busy is a misnomer. in synchronous peripheral mode this is really an acknowledge signal. 4.note that data starts to shift out serially on the dout pin 0.5 cclk periods after it was loaded in parallel. therefore, additional cclk pulses are clearly required after the last byte has been loaded. figure 34: synchronous peripheral mode programming switching characteristics 0 dout cclk 1 2 345 6 7 byte 0 byte 1 byte 0 out byte 1 out rdy/busy init 1 0 x6096 t ccl d0 - d7 t ic t cd t dc 1 2 3 description symbol min max units cclk init (high) setup time 1 t ic 5 m s d0 - d7 setup time 2 t dc 60 ns d0 - d7 hold time 3 t cd 0ns cclk high time t cch 50 ns cclk low time t ccl 60 ns cclk frequency f cc 8mhz
r xc5200 series field programmable gate arrays 7-120 november 5, 1998 (version 5.2) asynchronous peripheral mode write to fpga asynchronous peripheral mode uses the trailing edge of the logic and condition of ws and cs0 being low and rs and cs1 being high to accept byte-wide data from a micro- processor bus. in the lead fpga, this data is loaded into a double-buffered uart-like parallel-to-serial converter and is serially shifted into the internal logic. the lead fpga presents the preamble data (and all data that overflows the lead device) on its dout pin. the rdy/busy output from the lead fpga acts as a hand- shake signal to the microprocessor. rdy/busy goes low when a byte has been received, and goes high again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. a new write may be started immediately, as soon as the rdy/busy output has gone low, acknowledging receipt of the previous data. write may not be terminated until rdy/busy is high again for one cclk period. note that rdy/busy is pulled high with a high-impedance pull-up prior to init going high. the length of the busy signal depends on the activity in the uart. if the shift register was empty when the new byte was received, the busy signal lasts for only two cclk periods. if the shift register was still full when the new byte was received, the busy signal can be as long as nine cclk periods. note that after the last byte has been entered, only seven of its bits are shifted out. cclk remains high with dout equal to bit 6 (the next-to-last bit) of the last byte entered. the ready/busy handshake can be ignored if the delay from any one write to the end of the next write is guaran- teed to be longer than 10 cclk periods. status read the logic and condition of the cs0 , cs1 and rs inputs puts the device status on the data bus. ? d7 high indicates ready ? d7 low indicates busy ? d0 through d6 go unconditionally high it is mandatory that the whole start-up sequence be started and completed by one byte-wide input. otherwise, the pins used as write strobe or chip enable might become active outputs and interfere with the final byte transfer. if this transfer does not occur, the start-up sequence is not com- pleted all the way to the finish (point f in figure 25 on page 109 ). in this case, at worst, the internal reset is not released. at best, readback and boundary scan are inhibited. the length-count value, as generated by the software, ensures that these problems never occur. although rdy/busy is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. for this purpose, d7 represents the rdy/busy status when rs is low, ws is high, and the two chip select lines are both active. asynchronous peripheral mode is selected by a <101> on the mode pins (m2, m1, m0). address bus data bus address decode logic cs0 ... rdy/busy ws program d0? cclk dout din m2 m0 m1 n/c n/c n/c rs cs1 control signals init reprogram optional daisy-chained fpgas v cc done 8 x9006 3.3 k 4.7 k 4.7 k 3.3 k xc5200 asynchro- nous peripheral program cclk dout m2 m0 m1 init done xc5200/ xc4000e/ex slave figure 35: asynchronous peripheral mode circuit diagram
r november 5, 1998 (version 5.2) 7-121 xc5200 series field programmable gate arrays 7 notes: 1. configuration must be delayed until init pins of all daisy-chained fpgas are high. 2. the time from the end of ws to cclk cycle for the new byte of data depends on the completion of previous byte processing and the phase of internal timing generator for cclk. 3. cclk and dout timing is tested in slave mode. 4. t busy indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. the shortest t busy occurs when a byte is loaded into an empty parallel-to-serial converter. the longest t busy occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. this timing diagram shows very relaxed requirements. data need not be held beyond the rising edge of ws . rdy/busy will go active within 60 ns after the end of ws . a new write may be asserted immediately after rdy/busy goes low, but write may not be terminated until rdy/busy has been high for one cclk period. figure 36: asynchronous peripheral mode programming switching characteristics previous byte d6 d7 d0 d1 d2 1 t ca 2 t dc 4 t wtrb 3 t cd 6 t busy ready busy rs, cs0 ws, cs1 d7 ws/cs0 rs, cs1 d0-d7 cclk rdy/busy dout write to lca read status x6097 7 4 description symbol min max units write effective write time (cso , ws =low; rs , cs1=high 1t ca 100 ns din setup time 2 t dc 60 ns din hold time 3 t cd 0ns rdy rdy/busy delay after end of write or read 4t wtrb 60 ns rdy/busy active after beginning of read 760ns rdy/busy low output (note 4) 6 t busy 2 9 cclk periods
r xc5200 series field programmable gate arrays 7-122 november 5, 1998 (version 5.2) express mode express mode is similar to slave serial mode, except that data is processed one byte per cclk cycle instead of one bit per cclk cycle. an external source is used to drive cclk, while byte-wide data is loaded directly into the con- figuration data shift registers. a cclk frequency of 10 mhz is equivalent to an 80 mhz serial rate, because eight bits of configuration data are loaded per cclk cycle. express mode does not support crc error checking, but does support constant-field error checking. in express mode, an external signal drives the cclk input of the fpga device. the first byte of parallel configuration data must be available at the d inputs of the fpga a short setup time before the second rising cclk edge. subse- quent data bytes are clocked in on each consecutive rising cclk edge. if the first device is configured in express mode, additional devices may be daisy-chained only if every device in the chain is also configured in express mode. cclk pins are tied together and d0-d7 pins are tied together for all devices along the chain. a status signal is passed from dout to cs1 of successive devices along the chain. the lead device in the chain has its cs1 input tied high (or float- ing, since there is an internal pullup). frame data is accepted only when cs1 is high and the devices configu- ration memory is not already full. the status pin dout is pulled low two internal-oscillator cycles after init is recog- nized as high, and remains low until the devices configu- ration memory is full. dout is then pulled high to signal the next device in the chain to accept the configuration data on the d0-d7 bus. the done pins of all devices in the chain should be tied together, with one or more active internal pull-ups. if a large number of devices are included in the chain, deacti- vate some of the internal pull-ups, since the low-driving done pin of the last device in the chain must sink the cur- rent from all pull-ups in the chain. the done pull-up is activated by default. it can be deactivated using an option in the bitstream generation software. xc5200 devices in express mode are always synchronized to done. the device becomes active after done goes high. done is an open-drain output. with the done pins tied together, therefore, the external done signal stays low until all devices are configured, then all devices in the daisy chain become active simultaneously. if the done pin of a device is left unconnected, the device becomes active as soon as that device has been configured. express mode is selected by a <010> on the mode pins (m2, m1, m0). init cclk cclk xc5200 m0 m1 m2 cs1 d0-d7 data bus program init cclk program init dout done done dout to additional optional daisy-chained devices to additional optional daisy-chained devices note: m2, m1, m0 can be shorted to ground if not used as i/o optional daisy-chained xc5200 m0 m1 vcc vcc 4.7k 3.3 k m2 cs1 d0-d7 program x6611_01 8 8 8 figure 37: express mode circuit diagram
r november 5, 1998 (version 5.2) 7-123 xc5200 series field programmable gate arrays 7 note: if not driven by the preceding dout, cs1 must remain high until the device is fully configured. figure 38: express mode programming switching characteristics x5087 byte 0 cclk fpga filled 1 2 3 init t dc t cd t ic d0-d7 serial data out (dout) rdy/busy cs1 byte 1 byte 2 byte 3 internal init description symbol min max units cclk init (high) setup time required 1 t ic 5 m s din setup time required 2 t dc 30 ns din hold time required 3 t cd 0ns cclk high time t cch 30 ns cclk low time t ccl 30 ns cclk frequency f cc 10 mhz
r xc5200 series field programmable gate arrays 7-124 november 5, 1998 (version 5.2) notes : 1. a shaded table cell represents a 20-k w to 100-k w pull-up resistor before and during configuration. 2. (i) represents an input (o) represents an output. 3. init is an open-drain output during configuration. table 13. pin functions during configuration configuration mode: user operation slave <1:1:1> master-ser <0:0:0> syn.periph <0:1:1> asyn.periph <1:0:1> master-high <1:1:0> master-low <1:0:0> express <0:1:0> a16 a16 gck1-i/o a17 a17 i/o tdi tdi tdi tdi tdi tdi tdi tdi-i/o tck tck tck tck tck tck tck tck-i/o tms tms tms tms tms tms tms tms-i/o i/o m1 (high) (i) m1 (low) (i) m1 (high) (i) m1 (low) (i) m1 (high) (i) m1 (low) (i) m1 (high) (i) i/o m0 (high) (i) m0 (low) (i) m0 (high) (i) m0 (high) (i) m0 (low) (i) m0 (low) (i) m0 (low) (i) i/o m2 (high) (i) m2 (low) (i) m2 (low) (i) m2 (high) (i) m2 (high) (i) m2 (high) (i) m2 (low) (i) i/o gck2-i/o hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) i/o ldc (low)ldc (low)ldc (low)ldc (low)ldc (low)ldc (low)ldc (low) i/o init -error init -error init -error init -error init -error init -error init -error i/o i/o done done done done done done done done program (i) program (i) program (i) program (i) program (i) program (i) program (i) program data 7 (i) data 7 (i) data 7 (i) data 7 (i) data 7 (i) i/o gck3-i/o data 6 (i) data 6 (i) data 6 (i) data 6 (i) data 6 (i) i/o data 5 (i) data 5 (i) data 5 (i) data 5 (i) data 5 (i) i/o cso (i) i/o data 4 (i) data 4 (i) data 4 (i) data 4 (i) data 4 (i) i/o data 3 (i) data 3 (i) data 3 (i) data 3 (i) data 3 (i) i/o rs (i) i/o data 2 (i) data 2 (i) data 2 (i) data 2 (i) data 2 (i) i/o data 1 (i) data 1 (i) data 1 (i) data 1 (i) data 1 (i) i/o rdy/busy rdy/busy rclk rclk i/o din (i) din (i) data 0 (i) data 0 (i) data 0 (i) data 0 (i) data 0 (i) i/o dout dout dout dout dout dout dout i/o cclk (i) cclk (o) cclk (i) cclk (o) cclk (o) cclk (o) cclk (i) cclk (i) tdo tdo tdo tdo tdo tdo tdo tdo-i/o ws (i) a0 a0 i/o a1 a1 gck4-i/o cs1 (i) a2 a2 cs1 (i) i/o a3 a3 i/o a4 a4 i/o a5 a5 i/o a6 a6 i/o a7 a7 i/o a8 a8 i/o a9 a9 i/o a10 a10 i/o a11 a11 i/o a12 a12 i/o a13 a13 i/o a14 a14 i/o a15 a15 i/o all others
r november 5, 1998 (version 5.2) 7-125 xc5200 series field programmable gate arrays 7 configuration switching characteristics valid program init vcc pi t por t icck t cclk t cclk output or input m0, m1, m2 done response <300 ns <300 ns >300 ns re-program x1532 (required) i/o master modes description symbol min max units power-on-reset t por 215 ms program latency t pi 670 m s per clb column cclk (output) delay period (slow) period (fast) t icck t cclk t cclk 40 640 100 375 3000 375 m s ns ns slave and peripheral modes description symbol min max units power-on-reset t por 215 ms program latency t pi 670 m s per clb column cclk (input) delay (required) period (required) t icck t cclk 5 100 m s ns note: at power-up, v cc must rise from 2.0 to v cc min in less than 15 ms, otherwise delay configuration using program until v cc is valid.
r xc5200 series field programmable gate arrays 7-126 november 5, 1998 (version 5.2) xc5200 program readback switching characteristic guidelines testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are not measured directly. they are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. the following guidelines reflect worst-case values over the recommended operating conditions. note 1: timing parameters apply to all speed grades. note 2: rdbk.trig is high prior to finished, finished will trigger the first readback description symbol min max units rdbk.trig rdbk.trig setup to initiate and abort readback rdbk.trig hold to initiate and abort readback 1 2 t rtrc t rcrt 200 50 - - ns ns rdclk.1 rdbk.data delay rdbk.rip delay high time low time 7 6 5 4 t rcrd t rcrr t rch t rcl - - 250 250 250 250 500 500 ns ns ns ns rtrc t rcrt t 2 rcl t 4 rcrr t 6 rch t 5 rcrd t 7 dummy dummy rdbk.data rdbk.rip rdclk.i rdbk.trig finished internal net valid rtl t 3 x1790 valid 1
r november 5, 1998 (version 5.2) 7-127 xc5200 series field programmable gate arrays 7 xc5200 switching characteristics definition of terms in the following tables, some specifications may be designated as advance or preliminary. these terms are defined as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: specifications not identified as either advance or preliminary are to be considered final. 1 xc5200 operating conditions xc5200 dc characteristics over operating conditions xc5200 absolute maximum ratings 1. notwithstanding the definition of the above terms, all specifications are subject to change without notice. symbol description min max units v cc supply voltage relative to gnd commercial: 0 c to 85 c junction 4.75 5.25 v supply voltage relative to gnd industrial: -40 c to 100 c junction 4.5 5.5 v v iht high-level input voltage ttl configuration 2.0 v cc v v ilt low-level input voltage ttl configuration 0 0.8 v v ihc high-level input voltage cmos configuration 70% 100% v cc v ilc low-level input voltage cmos configuration 0 20% v cc t in input signal transition time 250 ns symbol description min max units v oh high-level output voltage @ i oh = -8.0 ma, v cc min 3.86 v v ol low-level output voltage @ i ol = 8.0 ma, v cc max 0.4 v i cco quiescent fpga supply current (note 1) 15 ma i il leakage current -10 +10 m a c in input capacitance (sample tested) 15 pf i rin pad pull-up (when selected) @ v in = 0v (sample tested) 0.02 0.30 ma note: 1. with no output current loads, all package pins at vcc or gnd, either ttl or cmos inputs, and the fpga configured with a tie option. symbol description units v cc supply voltage relative to gnd -0.5 to +7.0 v v in input voltage with respect to gnd -0.5 to v cc +0.5 v v ts voltage applied to 3-state output -0.5 to v cc +0.5 v t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature in plastic packages +125 c junction temperature in ceramic packages +150 c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability.
r xc5200 series field programmable gate arrays 7-128 november 5, 1998 (version 5.2) xc5200 global buffer switching characteristic guidelines testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines reflect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. xc5200 longline switching characteristic guidelines testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines reflect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. speed grade-6-5-4-3 description symbol device max (ns) max (ns) max (ns) max (ns) global signal distribution from pad through global buffer, to any clock (ck) t bufg xc5202 9.1 8.5 8.0 6.9 xc5204 9.3 8.7 8.2 7.6 xc5206 9.4 8.8 8.3 7.7 xc5210 9.4 8.8 8.5 7.7 xc5215 10.5 9.9 9.8 9.6 speed grade -6 -5 -4 -3 description symbol device max (ns) max (ns) max (ns) max (ns) tbuf driving a longline i to longline, while ts is low; i.e., buffer is constantly ac- tive t io xc5202 6.0 3.8 3.0 2.0 xc5204 6.4 4.1 3.2 2.3 xc5206 6.6 4.2 3.3 2.7 xc5210 6.6 4.2 3.3 2.9 xc5215 7.3 4.6 3.8 3.2 ts going low to longline going from floating high or low to active low or high t on xc5202 7.8 5.6 4.7 4.0 xc5204 8.3 5.9 4.9 4.3 xc5206 8.4 6.0 5.0 4.4 xc5210 8.4 6.0 5.0 4.4 xc5215 8.9 6.3 5.3 4.5 ts going high to tbuf going inactive, not driving longline t off xc52xx 3.0 2.8 2.6 2.4 note: 1. die-size-dependent parameters are based upon xc5215 characterization. production specifications will vary with array size. ts io tbuf
r november 5, 1998 (version 5.2) 7-129 xc5200 series field programmable gate arrays 7 xc5200 clb switching characteristic guidelines testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines reflect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. speed grade -6 -5 -4 -3 description symbol min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) combinatorial delays f inputs to x output t ilo 5.6 4.6 3.8 3.0 f inputs via transparent latch to q t ito 8.0 6.6 5.4 4.3 di inputs to do output (logic-cell feedthrough) t ido 4.3 3.5 2.8 2.4 f inputs via f5_mux to do output t imo 7.2 5.8 5.0 4.3 carry delays incremental delay per bit t cy 0.7 0.6 0.5 0.5 carry-in overhead from di t cydi 1.8 1.6 1.5 1.4 carry-in overhead from f t cyl 3.7 3.2 2.9 2.4 carry-out overhead to do t cyo 4.0 3.2 2.5 2.1 sequential delays clock (ck) to out (q) (flip-flop) t cko 5.8 4.9 4.0 4.0 gate (latch enable) going active to out (q) t go 9.2 7.4 5.9 5.5 set-up time before clock (ck) f inputs t ick 2.3 1.8 1.4 1.3 f inputs via f5_mux t mick 3.8 3.0 2.5 2.4 di input t dick 0.8 0.5 0.4 0.4 ce input t eick 1.6 1.2 0.9 0.9 hold times after clock (ck) f inputs t cki 00 0 0 f inputs via f5_mux t ckmi 00 0 0 di input t ckdi 00 0 0 ce input t ckei 00 0 0 clock widths clock high time t ch 6.0 6.0 6.0 6.0 clock low time t cl 6.0 6.0 6.0 6.0 toggle frequency (mhz) (note 3) f tog 83 83 83 83 reset delays width (high) t clrw 6.0 6.0 6.0 6.0 delay from clr to q (flip-flop) t clr 7.7 6.3 5.1 4.0 delay from clr to q (latch) t clrl 6.5 5.2 4.2 3.0 global reset delays width (high) t gclrw 6.0 6.0 6.0 6.0 delay from internal gr to q t gclr 14.7 12.1 9.1 8.0 note: 1. the clb k to q output delay (t cko ) of any clb, plus the shortest possible interconnect delay, is always longer than the data in hold-time requirement (t ckdi ) of any clb on the same die. 2. timing is based upon the xc5215 device. for other devices, see timing calculator. 3. maximum flip-flop toggle rate for export control purposes.
r xc5200 series field programmable gate arrays 7-130 november 5, 1998 (version 5.2) xc5200 guaranteed input and output parameters (pin-to-pin) all values listed below are tested directly, and guaranteed over the operating conditions. the same parameters can also be derived indirectly from the global buffer specifications. the delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. when there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. speed grade -6 -5 -4 -3 description symbol device max (ns) max (ns) max (ns) max (ns) global clock to output pad (fast) t ickof (max) xc5202 16.9 15.1 10.9 9.8 xc5204 17.1 15.3 11.3 9.9 xc5206 17.2 15.4 11.9 10.8 xc5210 17.2 15.4 12.8 11.2 xc5215 19.0 17.0 12.8 11.7 global clock to output pad (slew-limited) t icko (max) xc5202 21.4 18.7 12.6 11.5 xc5204 21.6 18.9 13.3 11.9 xc5206 21.7 19.0 13.6 12.5 xc5210 21.7 19.0 15.0 12.9 xc5215 24.3 21.2 15.0 13.1 input set-up time (no delay) to clb flip-flop t psuf (min) xc5202 2.5 2.0 1.9 1.9 xc5204 2.3 1.9 1.9 1.9 xc5206 2.2 1.9 1.9 1.9 xc5210 2.2 1.9 1.9 1.8 xc5215 2.0 1.8 1.7 1.7 input hold time (no delay) to clb flip-flop t phf (min) xc5202 3.8 3.8 3.5 3.5 xc5204 3.9 3.9 3.8 3.6 xc5206 4.4 4.4 4.4 4.3 xc5210 5.1 5.1 4.9 4.8 xc5215 5.8 5.8 5.7 5.6 input set-up time (with delay) to clb flip-flop di input t psu xc5202 7.3 6.6 6.6 6.6 xc5204 7.3 6.6 6.6 6.6 xc5206 7.2 6.5 6.4 6.3 xc5210 7.2 6.5 6.0 6.0 xc5215 6.8 5.7 5.7 5.7 input set-up time (with delay) to clb flip-flop f input t psu l (min) xc5202 8.8 7.7 7.5 7.5 xc5204 8.6 7.5 7.5 7.5 xc5206 8.5 7.4 7.4 7.4 xc5210 8.5 7.4 7.4 7.3 xc5215 8.5 7.4 7.4 7.2 input hold time (with delay) to clb flip-flop t ph (min) xc52xx 0 000 note: 1. these measurements assume that the clb flip-flop uses a direct interconnect to or from the iob. the inreg/ outreg properties, or xact-performance, can be used to assure that direct connects are used. t psu applies only to the clb input di that bypasses the look-up table, which only offers direct connects to iobs on the left and right edges of the die. t psul applies to the clb inputs f that feed the look-up table, which offers direct connect to iobs on all four edges, as do the clb q outputs. 2. when testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. global clock-to-output delay q . . . . direct connect iob clb fast bufg global clock-to-output delay q . . . . direct connect iob clb bufg input set-up & hold time f, d i iob (nodelay) direct connect clb bufg input set-up & hold time direct connect clb iob (nodelay) f,di bufg input set-up & hold time iob direct connect clb di bufg input set-up & hold time iob direct connect clb bufg f input set-up & hold time iob direct connect clb bufg f, d i
r november 5, 1998 (version 5.2) 7-131 xc5200 series field programmable gate arrays 7 xc5200 iob switching characteristic guidelines testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. the following guidelines reflect worst-case values over the recommended operating conditions. for more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. speed grade -6 -5 -4 -3 description symbol max (ns) max (ns) max (ns) max (ns) input propagation delays from cmos or ttl levels pad to i (no delay) t pi 5.7 5.0 4.8 3.3 pad to i (with delay) t pid 11.4 10.2 10.2 9.5 output propagation delays to cmos or ttl levels output (o) to pad (fast) t opf 4.6 4.5 4.5 3.5 output (o) to pad (slew-limited) t ops 9.5 8.4 8.0 5.0 from clock (ck) to output pad (fast), using direct connect between q and output (o) t okpof 10.1 9.3 8.3 7.5 from clock (ck) to output pad (slew-limited), using direct connect be- tween q and output (o) t okpos 14.9 13.1 11.8 10.0 3-state to pad active (fast) t tsonf 5.6 5.2 4.9 4.6 3-state to pad active (slew-limited) t tsons 10.4 9.0 8.3 6.0 internal gts to pad active t gts 17.7 15.9 14.7 13.5 note: 1. timing is measured at pin threshold, with 50-pf external capacitance loads. slew-limited output rise/fall times are approximately two times longer than fast output rise/fall times. 2. unused and unbonded iobs are configured by default as inputs with internal pull-up resistors. 3. timing is based upon the xc5215 device. for other devices, see timing calculator.
r xc5200 series field programmable gate arrays 7-132 november 5, 1998 (version 5.2) xc5200 boundary scan (jtag) switching characteristic guidelines the following guidelines reflect worst-case values over the recommended operating conditions. they are expressed in units of nanoseconds and apply to all xc5200 devices unless otherwise noted. speed grade -6 -5 -4 -3 description symbol min max min max min max min max setup and hold input (tdi) to clock (tck) setup time input (tdi) to clock (tck) hold time input (tms) to clock (tck) setup time input (tms) to clock (tck) hold time t tditck t tcktdi t tmstck t tcktms 30.0 0 15.0 0 30.0 0 15.0 0 30.0 0 15.0 0 30.0 0 15.0 0 propagation delay clock (tck) to pad (tdo) t tckpo 30.0 30.0 30.0 30.0 clock clock (tck) high clock (tck) low t tckh t tckl 30.0 30.0 30.0 30.0 30.0 30.0 30.0 30.0 f max (mhz) f max 10.0 10.0 10.0 10.0 note 1: input pad setup and hold times are specified with respect to the internal clock.
r november 5, 1998 (version 5.2) 7-133 xc5200 series field programmable gate arrays 7 device-specific pinout tables device-specific tables include all packages for each xc5200-series device. they follow the pad locations around the die, and include boundary scan register locations. pin locations for xc5202 devices the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc5200 series data sheet for availability information. pin description vq64* pc84 pq100 vq100 tq144 pg156 boundary scan order vcc - 2 92 89 128 h3 - 1. i/o (a8) 57 3 93 90 129 h1 51 2. i/o (a9) 58 4 94 91 130 g1 54 3. i/o - - 95 92 131 g2 57 4. i/o - - 96 93 132 g3 63 5. i/o (a10) - 5 97 94 133 f1 66 6. i/o (a11) 59 6 98 95 134 f2 69 gnd - - - - 137 f3 - 7. i/o (a12) 60 7 99 96 138 e3 78 8. i/o (a13) 61 8 100 97 139 c1 81 9. i/o (a14) 62 9 1 98 142 b1 90 10. i/o (a15) 63 10 2 99 143 b2 93 vcc 64113100144c3 - gnd - 12 4 1 1 c4 - 11. gck1 (a16, i/o) 1 13 5 2 2 b3 102 12. i/o (a17) 2 14 6 3 3 a1 105 13. i/o (tdi) 3 15 7 4 6 b4 111 14. i/o (tck) 4 16 8 5 7 a3 114 gnd - - - - 8 c6 - 15. i/o (tms) 5 17 9 6 11 a5 117 16. i/o 6 18 10 7 12 c7 123 17. i/o - - - - 13 b7 126 18. i/o - - 11 8 14 a6 129 19. i/o - 19 12 9 15 a7 135 20. i/o 7 20 13 10 16 a8 138 gnd 8 21 14 11 17 c8 - vcc 9 22 15 12 18 b8 - 21. i/o - 23 16 13 19 c9 141 22. i/o 10 24 17 14 20 b9 147 23. i/o - 18 15 21 a9 150 24. i/o - - - 22 b10 153 25. i/o - 25 19 16 23 c10 159 26. i/o 11 26 20 17 24 a10 162 gnd - - - 27 c11 - 27. i/o 12 27 21 18 28 b12 165 28. i/o - 22 19 29 a13 171 29. i/o 13 28 23 20 32 b13 174 30. i/o 14 29 24 21 33 b14 177 31. m1 (i/o) 15 30 25 22 34 a15 186 gnd - 31 26 23 35 c13 - 32. m0 (i/o) 16 32 27 24 36 a16 189 vcc - 33 28 25 37 c14 - 33. m2 (i/o) 17 34 29 26 38 b15 192 34. gck2 (i/o) 18 35 30 27 39 b16 195
r xc5200 series field programmable gate arrays 7-134 november 5, 1998 (version 5.2) 35. i/o (hdc) 19 36 31 28 40 d14 204 36. i/o - - 32 29 43 e14 207 37. i/o (ldc) 20 37 33 30 44 c16 210 gnd - - - - 45 f14 - 38. i/o - 38 34 31 48 f16 216 39. i/o 21 39 35 32 49 g14 219 40. i/o - - 36 33 50 g15 222 41. i/o - - 37 34 51 g16 228 42. i/o 22 40 38 35 52 h16 231 43. i/o (err , init ) 23 41 39 36 53 h15 234 vcc 24 42 40 37 54 h14 - gnd 25 43 41 38 55 j14 - 44. i/o 26 44 42 39 56 j15 240 45. i/o 27 45 43 40 57 j16 243 46. i/o - - 44 41 58 k16 246 47. i/o - - 45 42 59 k15 252 48. i/o 28 46 46 43 60 k14 255 49. i/o 29 47 47 44 61 l16 258 gnd - - - - 64 l14 - 50. i/o - 48 48 45 65 p16 264 51. i/o 30 49 49 46 66 m14 267 52. i/o - 50 50 47 69 n14 276 53. i/o 31 51 51 48 70 r16 279 gnd - 52 52 49 71 p14 - done 32 53 53 50 72 r15 - vcc 33 54 54 51 73 p13 - prog 34 55 55 52 74 r14 - 54. i/o (d7) 35 56 56 53 75 t16 288 55. gck3 (i/o) 36 57 57 54 76 t15 291 56. i/o (d6) 37 58 58 55 79 t14 300 57. i/o - - 59 56 80 t13 303 gnd - - - - 81 p11 - 58. i/o (d5) 38 59 60 57 84 t10 306 59. i/o (cs0 ) - 60 61 58 85 p10 312 60. i/o - - 62 59 86 r10 315 61. i/o - - 63 60 87 t9 318 62. i/o (d4) 39 61 64 61 88 r9 324 63. i/o - 62 65 62 89 p9 327 vcc 40 63 66 63 90 r8 - gnd 41 64 67 64 91 p8 - 64. i/o (d3) 42 65 68 65 92 t8 336 65. i/o (rs ) 43 66 69 66 93 t7 339 66. i/o - - 70 67 94 t6 342 67. i/o - - - - 95 r7 348 68. i/o (d2) 44 67 71 68 96 p7 351 69. i/o - 68 72 69 97 t5 360 gnd - - - - 100 p6 - 70. i/o (d1) 45 69 73 70 101 t3 363 71. i/o (rclk-busy /rdy) - 70 74 71 102 p5 366 72. i/o (d0, din) 46 71 75 72 105 p4 372 73. i/o (dout) 47 72 76 73 106 t2 375 pin description vq64* pc84 pq100 vq100 tq144 pg156 boundary scan order
r november 5, 1998 (version 5.2) 7-135 xc5200 series field programmable gate arrays 7 * vq64 package supports master serial, slave serial, and express configuration modes only. additional no connect (n.c.) connections on tq144 package notes: boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 1056 = bscan.upd pin locations for xc5204 devices the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc5200 series data sheet for availability information. cclk 48 73 77 74 107 r2 - vcc - 74 78 75 108 p3 - 74. i/o (tdo) 49 75 79 76 109 t1 0 gnd - 76 80 77 110 n3 - 75. i/o (a0, ws )50778178111r1 9 76. gck4 (a1, i/o) 51 78 82 79 112 p2 15 77. i/o (a2, cs1) 52 79 83 80 115 p1 18 78. i/o (a3) - 80 84 81 116 n1 21 gnd - - - - 118 l3 - 79. i/o (a4) - 81 85 82 121 k3 27 80. i/o (a5) 53 82 86 83 122 k2 30 81. i/o - - 87 84 123 k1 33 82. i/o - - 88 85 124 j1 39 83. i/o (a6) 54 83 89 86 125 j2 42 84. i/o (a7) 55 84 90 87 126 j3 45 gnd 56 1 91 88 127 h2 - tq144 135 9 41 67 98 117 136 10 42 68 99 119 140 25 46 77 103 120 141 26 47 78 104 4 30 62 82 113 5 31 63 83 114 pin description pc84 pq100 vq100 tq144 pg156 pq160 boundary scan order vcc 2 92 89 128 h3 142 - 1. i/o (a8) 3 93 90 129 h1 143 78 2. i/o (a9) 4 94 91 130 g1 144 81 3. i/o - 95 92 131 g2 145 87 4. i/o - 96 93 132 g3 146 90 5. i/o (a10) 5 97 94 133 f1 147 93 6. i/o (a11) 6 98 95 134 f2 148 99 7. i/o - - - 135 e1 149 102 8. i/o - - - 136 e2 150 105 gnd - - - 137 f3 151 - 9. i/o - - - - d1 152 111 10. i/o - - - - d2 153 114 11. i/o (a12) 7 99 96 138 e3 154 117 12. i/o (a13) 8 100 97 139 c1 155 123 13. i/o - - - 140 c2 156 126 pin description vq64* pc84 pq100 vq100 tq144 pg156 boundary scan order
r xc5200 series field programmable gate arrays 7-136 november 5, 1998 (version 5.2) 14. i/o - - - 141 d3 157 129 15. i/o (a14) 9 1 98 142 b1 158 138 16. i/o (a15) 10 2 99 143 b2 159 141 vcc 11 3 100 144 c3 160 - gnd 12 4 1 1 c4 1 - 17. gck1 (a16, i/o) 13 5 2 2 b3 2 150 18. i/o (a17) 14 6 3 3 a1 3 153 19. i/o - - - 4 a2 4 159 20. i/o - - - 5 c5 5 162 21. i/o (tdi) 15 7 4 6 b4 6 165 22. i/o (tck) 16 8 5 7 a3 7 171 gnd - - - 8 c6 10 - 23. i/o - - - 9 b5 11 174 24. i/o - - - 10 b6 12 177 25. i/o (tms) 17 9 6 11 a5 13 180 26. i/o 18 10 7 12 c7 14 183 27. i/o - - - 13 b7 15 186 28. i/o - 11 8 14 a6 16 189 29. i/o 19 12 9 15 a7 17 195 30. i/o 20 13 10 16 a8 18 198 gnd 21141117c819 - vcc 22151218b820 - 31. i/o 23 16 13 19 c9 21 201 32. i/o 24 17 14 20 b9 22 207 33. i/o - 18 15 21 a9 23 210 34. i/o - - - 22 b10 24 213 35. i/o 25 19 16 23 c10 25 219 36. i/o 26 20 17 24 a10 26 222 37. i/o - - - 25 a11 27 225 38. i/o - - - 26 b11 28 231 gnd - - - 27 c11 29 - 39. i/o 27 21 18 28 b12 32 234 40. i/o - 22 19 29 a13 33 237 41. i/o - - - 30 a14 34 240 42. i/o - - - 31 c12 35 243 43. i/o 28 23 20 32 b13 36 246 44. i/o 29 24 21 33 b14 37 249 45. m1 (i/o) 30 25 22 34 a15 38 258 gnd 31262335c1339 - 46. m0 (i/o) 32 27 24 36 a16 40 261 vcc 33282537c1441 - 47. m2 (i/o) 34 29 26 38 b15 42 264 48. gck2 (i/o) 35 30 27 39 b16 43 267 49. i/o (hdc) 36 31 28 40 d14 44 276 50. i/o - - - 41 c15 45 279 51. i/o - - - 42 d15 46 282 52. i/o - 32 29 43 e14 47 288 53. i/o (ldc) 37 33 30 44 c16 48 291 54. i/o - - - - e15 49 294 55. i/o - - - - d16 50 300 gnd - - - 45 f14 51 - 56. i/o - - - 46 f15 52 303 pin description pc84 pq100 vq100 tq144 pg156 pq160 boundary scan order
r november 5, 1998 (version 5.2) 7-137 xc5200 series field programmable gate arrays 7 57. i/o - - - 47 e16 53 306 58. i/o 38 34 31 48 f16 54 312 59. i/o 39 35 32 49 g14 55 315 60. i/o - 36 33 50 g15 56 318 61. i/o - 37 34 51 g16 57 324 62. i/o 40 38 35 52 h16 58 327 63. i/o (err , init ) 41 39 36 53 h15 59 330 vcc 42403754h1460 - gnd 43413855j1461 - 64. i/o 44 42 39 56 j15 62 336 65. i/o 45 43 40 57 j16 63 339 66. i/o - 44 41 58 k16 64 348 67. i/o - 45 42 59 k15 65 351 68. i/o 46 46 43 60 k14 66 354 69. i/o 47 47 44 61 l16 67 360 70. i/o - - - 62 m16 68 363 71. i/o - - - 63 l15 69 366 gnd - - - 64 l14 70 - 72. i/o - - - - n16 71 372 73. i/o - - - - m15 72 375 74. i/o 48 48 45 65 p16 73 378 75. i/o 49 49 46 66 m14 74 384 76. i/o - - - 67 n15 75 387 77. i/o - - - 68 p15 76 390 78. i/o 50 50 47 69 n14 77 396 79. i/o 51 51 48 70 r16 78 399 gnd 52524971p1479 - done 53 53 50 72 r15 80 - vcc 54545173p1381 - prog 55 55 52 74 r14 82 - 80. i/o (d7) 56 56 53 75 t16 83 408 81. gck3 (i/o) 57 57 54 76 t15 84 411 82. i/o - - - 77 r13 85 420 83. i/o - - - 78 p12 86 423 84. i/o (d6) 58 58 55 79 t14 87 426 85. i/o - 59 56 80 t13 88 432 gnd - - - 81 p11 91 - 86. i/o - - - 82 r11 92 435 87. i/o - - - 83 t11 93 438 88. i/o (d5) 59 60 57 84 t10 94 444 89. i/o (cs0 ) 60 61 58 85 p10 95 447 90. i/o - 62 59 86 r10 96 450 91. i/o - 63 60 87 t9 97 456 92. i/o (d4) 61 64 61 88 r9 98 459 93. i/o 62 65 62 89 p9 99 462 vcc 63666390r8100 - gnd 64676491p8101 - 94. i/o (d3) 65 68 65 92 t8 102 468 95. i/o (rs ) 66 69 66 93 t7 103 471 96. i/o - 70 67 94 t6 104 474 97. i/o - - - 95 r7 105 480 98. i/o (d2) 67 71 68 96 p7 106 483 pin description pc84 pq100 vq100 tq144 pg156 pq160 boundary scan order
r xc5200 series field programmable gate arrays 7-138 november 5, 1998 (version 5.2) additional no connect (n.c.) connections for pq160 package notes: boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 1056 = bscan.upd 99. i/o 68 72 69 97 t5 107 486 100. i/o - - - 98 r6 108 492 101. i/o - - - 99 t4 109 495 gnd - - - 100 p6 110 - 102. i/o (d1) 69 73 70 101 t3 113 498 103. i/o (rclk-busy /rdy) 70 74 71 102 p5 114 504 104. i/o - - - 103 r4 115 507 105. i/o - - - 104 r3 116 510 106. i/o (d0, din) 71 75 72 105 p4 117 516 107. i/o (dout) 72 76 73 106 t2 118 519 cclk 73 77 74 107 r2 119 - vcc 74 78 75 108 p3 120 - 108. i/o (tdo) 75 79 76 109 t1 121 0 gnd 76 80 77 110 n3 122 - 109. i/o (a0, ws ) 77 81 78 111 r1 123 9 110. gck4 (a1, i/o) 78 82 79 112 p2 124 15 111. i/o - - - 113 n2 125 18 112. i/o - - - 114 m3 126 21 113. i/o (a2, cs1) 79 83 80 115 p1 127 27 114. i/o (a3) 80 84 81 116 n1 128 30 115. i/o - - - 117 m2 129 33 116. i/o - - - - m1 130 39 gnd - - - 118 l3 131 - 117. i/o - - - 119 l2 132 42 118. i/o - - - 120 l1 133 45 119. i/o (a4) 81 85 82 121 k3 134 51 120. i/o (a5) 82 86 83 122 k2 135 54 121. i/o - 87 84 123 k1 137 57 122. i/o - 88 85 124 j1 138 63 123. i/o (a6) 83 89 86 125 j2 139 66 124. i/o (a7) 84 90 87 126 j3 140 69 gnd 1 91 88 127 h2 141 - pq160 83089111136 93190112 pin description pc84 pq100 vq100 tq144 pg156 pq160 boundary scan order
r november 5, 1998 (version 5.2) 7-139 xc5200 series field programmable gate arrays 7 pin locations for xc5206 devices the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc5200 series data sheet for availability information. pin description pc84 pq100 vq100 tq144 pq160 tq176 pg191 pq208 boundary scan order vcc 2 92 89 128 142 155 j4 183 - 1. i/o (a8) 3 93 90 129 143 156 j3 184 87 2. i/o (a9) 4 94 91 130 144 157 j2 185 90 3. i/o - 95 92 131 145 158 j1 186 93 4. i/o - 96 93 132 146 159 h1 187 99 5. i/o - - - - - 160 h2 188 102 6. i/o - - - - - 161 h3 189 105 7. i/o (a10) 5 97 94 133 147 162 g1 190 111 8. i/o (a11) 6 98 95 134 148 163 g2 191 114 9. i/o - - - 135 149 164 f1 192 117 10. i/o - - - 136 150 165 e1 193 123 gnd - - - 137 151 166 g3 194 - 11. i/o - - - - 152 168 c1 197 126 12. i/o - - - - 153 169 e2 198 129 13. i/o (a12) 7 99 96 138 154 170 f3 199 138 14. i/o (a13) 8 100 97 139 155 171 d2 200 141 15. i/o - - - 140 156 172 b1 201 150 16. i/o - - - 141 157 173 e3 202 153 17. i/o (a14) 9 1 98 142 158 174 c2 203 162 18. i/o (a15) 10 2 99 143 159 175 b2 204 165 vcc 11 3 100 144 160 176 d3 205 - gnd 1241111d42 - 19. gck1 (a16, i/o) 13 5 2 2 2 2 c3 4 174 20. i/o (a17) 14 6 3 3 3 3 c4 5 177 21. i/o - - - 4 4 4 b3 6 183 22. i/o - - - 5 5 5 c5 7 186 23.i/o (tdi) 1574666a28 189 24.i/o (tck) 1685777b49 195 25. i/o - - - - 8 8 c6 10 198 26. i/o - - - - 9 9 a3 11 201 gnd - - - 8 10 10 c7 14 - 27. i/o - - - 9 11 11 a4 15 207 28. i/o - - - 10 12 12 a5 16 210 29. i/o (tms) 17 9 6 11 13 13 b7 17 213 30. i/o 18 10 7 12 14 14 a6 18 219 31. i/o - - - - - 15 c8 19 222 32. i/o - - - - - 16 a7 20 225 33. i/o - - - 13 15 17 b8 21 234 34.i/o - 118141618a822 237 35. i/o 19 12 9 15 17 19 b9 23 246 36. i/o 20 13 10 16 18 20 c9 24 249 gnd 21 1411171921d925 - vcc 22 1512182022d1026 - 37. i/o 23 16 13 19 21 23 c10 27 255 38. i/o 24 17 14 20 22 24 b10 28 258 39.i/o - 1815212325a929 261 40. i/o - - - 22 24 26 a10 30 267 41. i/o - - - - - 27 a11 31 270
r xc5200 series field programmable gate arrays 7-140 november 5, 1998 (version 5.2) 42. i/o - - - - - 28 c11 32 273 43. i/o 25 19 16 23 25 29 b11 33 279 44. i/o 26 20 17 24 26 30 a12 34 282 45. i/o - - - 25 27 31 b12 35 285 46. i/o - - - 26 28 32 a13 36 291 gnd - - - 27 29 33 c12 37 - 47. i/o - - - - 30 34 a15 40 294 48. i/o - - - - 31 35 c13 41 297 49. i/o 27 21 18 28 32 36 b14 42 303 50. i/o - 22 19 29 33 37 a16 43 306 51. i/o - - - 30 34 38 b15 44 309 52. i/o - - - 31 35 39 c14 45 315 53. i/o 28 23 20 32 36 40 a17 46 318 54. i/o 29 24 21 33 37 41 b16 47 321 55. m1 (i/o) 30 25 22 34 38 42 c15 48 330 gnd 31 2623353943d1549 - 56. m0 (i/o) 32 27 24 36 40 44 a18 50 333 vcc 33 2825374145d1655 - 57. m2 (i/o) 34 29 26 38 42 46 c16 56 336 58. gck2 (i/o) 35 30 27 39 43 47 b17 57 339 59. i/o (hdc) 36 31 28 40 44 48 e16 58 348 60. i/o - - - 41 45 49 c17 59 351 61. i/o - - - 42 46 50 d17 60 354 62. i/o - 32 29 43 47 51 b18 61 360 63. i/o (ldc) 37 33 30 44 48 52 e17 62 363 64. i/o - - - - 49 53 f16 63 372 65. i/o - - - - 50 54 c18 64 375 gnd - - - 45 51 55 g16 67 - 66. i/o - - - 46 52 56 e18 68 378 67. i/o - - - 47 53 57 f18 69 384 68. i/o 38 34 31 48 54 58 g17 70 387 69. i/o 39 35 32 49 55 59 g18 71 390 70. i/o - - - - - 60 h16 72 396 71. i/o - - - - - 61 h17 73 399 72. i/o - 36 33 50 56 62 h18 74 402 73.i/o - 3734515763j1875 408 74. i/o 40 38 35 52 58 64 j17 76 411 75. i/o (err , init )41 3936535965j1677 414 vcc 42 4037546066j1578 - gnd 43 4138556167k1579 - 76. i/o 44 42 39 56 62 68 k16 80 420 77. i/o 45 43 40 57 63 69 k17 81 423 78. i/o - 44 41 58 64 70 k18 82 426 79.i/o - 4542596571l1883 432 80. i/o - - - - - 72 l17 84 435 81. i/o - - - - - 73 l16 85 438 82. i/o 46 46 43 60 66 74 m18 86 444 83. i/o 47 47 44 61 67 75 m17 87 447 84. i/o - - - 62 68 76 n18 88 450 85. i/o - - - 63 69 77 p18 89 456 gnd - - - 64 70 78 m16 90 - 86. i/o - - - - 71 79 t18 93 459 pin description pc84 pq100 vq100 tq144 pq160 tq176 pg191 pq208 boundary scan order
r november 5, 1998 (version 5.2) 7-141 xc5200 series field programmable gate arrays 7 87. i/o - - - - 72 80 p17 94 468 88. i/o 48 48 45 65 73 81 n16 95 471 89. i/o 49 49 46 66 74 82 t17 96 480 90. i/o - - - 67 75 83 r17 97 483 91. i/o - - - 68 76 84 p16 98 486 92. i/o 50 50 47 69 77 85 u18 99 492 93. i/o 51 51 48 70 78 86 t16 100 495 gnd 52 52 49 71 79 87 r16 101 - done 53 53 50 72 80 88 u17 103 - vcc 54 54 51 73 81 89 r15 106 - prog 55 55 52 74 82 90 v18 108 - 94. i/o (d7) 56 56 53 75 83 91 t15 109 504 95. gck3 (i/o) 57 57 54 76 84 92 u16 110 507 96. i/o - - - 77 85 93 t14 111 516 97. i/o - - - 78 86 94 u15 112 519 98. i/o (d6) 58 58 55 79 87 95 v17 113 522 99. i/o - 59 56 80 88 96 v16 114 528 100. i/o - - - - 89 97 t13 115 531 101. i/o - - - - 90 98 u14 116 534 gnd - - - 81 91 99 t12 119 - 102. i/o - - - 82 92 100 u13 120 540 103. i/o - - - 83 93 101 v13 121 543 104. i/o (d5) 59 60 57 84 94 102 u12 122 552 105. i/o (cs0 ) 60 61 58 85 95 103 v12 123 555 106. i/o - - - - - 104 t11 124 558 107. i/o - - - - - 105 u11 125 564 108. i/o - 62 59 86 96 106 v11 126 567 109. i/o - 63 60 87 97 107 v10 127 570 110. i/o (d4) 61 64 61 88 98 108 u10 128 576 111. i/o 62 65 62 89 99 109 t10 129 579 vcc 63 66 63 90 100 110 r10 130 - gnd 64 67 64 91 101 111 r9 131 - 112. i/o (d3) 65 68 65 92 102 112 t9 132 588 113. i/o (rs ) 66 69 66 93 103 113 u9 133 591 114. i/o - 70 67 94 104 114 v9 134 600 115. i/o - - - 95 105 115 v8 135 603 116. i/o - - - - - 116 u8 136 612 117. i/o - - - - - 117 t8 137 615 118. i/o (d2) 67 71 68 96 106 118 v7 138 618 119. i/o 68 72 69 97 107 119 u7 139 624 120. i/o - - - 98 108 120 v6 140 627 121. i/o - - - 99 109 121 u6 141 630 gnd - - - 100 110 122 t7 142 - 122. i/o - - - - 111 123 u5 145 636 123. i/o - - - - 112 124 t6 146 639 124. i/o (d1) 69 73 70 101 113 125 v3 147 642 125. i/o (rclk-busy /rd y) 70 74 71 102 114 126 v2 148 648 126. i/o - - - 103 115 127 u4 149 651 127. i/o - - - 104 116 128 t5 150 654 128. i/o (d0, din) 71 75 72 105 117 129 u3 151 660 129. i/o (dout) 72 76 73 106 118 130 t4 152 663 pin description pc84 pq100 vq100 tq144 pq160 tq176 pg191 pq208 boundary scan order
r xc5200 series field programmable gate arrays 7-142 november 5, 1998 (version 5.2) additional no connect (n.c.) connections for pq208 and tq176 packages notes: boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 1056 = bscan.upd pin locations for xc5210 devices the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc5200 series data sheet for availability information. cclk 73 77 74 107 119 131 v1 153 - vcc 74 78 75 108 120 132 r4 154 - 130. i/o (tdo) 75 79 76 109 121 133 u2 159 - gnd 76 80 77 110 122 134 r3 160 - 131. i/o (a0, ws ) 77 81 78 111 123 135 t3 161 9 132. gck4 (a1, i/o) 78 82 79 112 124 136 u1 162 15 133. i/o - - - 113 125 137 p3 163 18 134. i/o - - - 114 126 138 r2 164 21 135. i/o (a2, cs1) 79 83 80 115 127 139 t2 165 27 136. i/o (a3) 80 84 81 116 128 140 n3 166 30 137. i/o - - - 117 129 141 p2 167 33 138. i/o - - - - 130 142 t1 168 42 gnd - - - 118 131 143 m3 171 - 139. i/o - - - 119 132 144 p1 172 45 140. i/o - - - 120 133 145 n1 173 51 141. i/o (a4) 81 85 82 121 134 146 m2 174 54 142. i/o (a5) 82 86 83 122 135 147 m1 175 57 143. i/o - - - - - 148 l3 176 63 144. i/o - - - - 136 149 l2 177 66 145. i/o - 87 84 123 137 150 l1 178 69 146. i/o - 88 85 124 138 151 k1 179 75 147. i/o (a6) 83 89 86 125 139 152 k2 180 78 148. i/o (a7) 84 90 87 126 140 153 k3 181 81 gnd 1 91 88 127 141 154 k4 182 - pq208 tq176 195 1 39 65 104 143 158 167 196 3 51 66 105 144 169 206 12 52 91 107 155 170 207 13 53 92 117 156 208 38 54 102 118 157 pin description pc84 pq100 vq100 tq144 pq160 tq176 pg191 pq208 boundary scan order pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order vcc 2 128 142 155 183 j4 vcc* 212 - 1. i/o (a8) 3 129 143 156 184 j3 e8 213 111 2. i/o (a9) 4 130 144 157 185 j2 b7 214 114 3. i/o - 131 145 158 186 j1 a7 215 117 4. i/o - 132 146 159 187 h1 c7 216 123 5. i/o - - - 160 188 h2 d7 217 126 6. i/o - - - 161 189 h3 e7 218 129
r november 5, 1998 (version 5.2) 7-143 xc5200 series field programmable gate arrays 7 7. i/o (a10) 5 133 147 162 190 g1 a6 220 135 8. i/o (a11) 6 134 148 163 191 g2 b6 221 138 vcc ------vcc*222 - 9. i/o - - - - - h4 c6 223 141 10. i/o - - - - - g4 f7 224 150 11. i/o - 135 149 164 192 f1 a5 225 153 12. i/o - 136 150 165 193 e1 b5 226 162 gnd - 137 151 166 194 g3 gnd* 227 - 13. i/o - - - - 195 f2 d6 228 165 14. i/o - - - 167 196 d1 c5 229 171 15. i/o - - 152 168 197 c1 a4 230 174 16. i/o - - 153 169 198 e2 e6 231 177 17. i/o (a12) 7 138 154 170 199 f3 b4 232 183 18. i/o (a13) 8 139 155 171 200 d2 d5 233 186 19. i/o - - - - - f4 a3 234 189 20. i/o - - - - - e4 c4 235 195 21. i/o - 140 156 172 201 b1 b3 236 198 22. i/o - 141 157 173 202 e3 f6 237 201 23. i/o (a14) 9 142 158 174 203 c2 a2 238 210 24. i/o (a15) 10 143 159 175 204 b2 c3 239 213 vcc 11 144 160 176 205 d3 vcc* 240 - gnd 12 1 1 1 2 d4 gnd* 1 - 25. gck1 (a16, i/o) 13 2 2 2 4 c3 d4 2 222 26. i/o (a17) 14 3 3 3 5 c4 b1 3 225 27. i/o - 4 4 4 6 b3 c2 4 231 28. i/o - 5 5 5 7 c5 e5 5 234 29. i/o (tdi) 15 6 6 6 8 a2 d3 6 237 30. i/o (tck) 16 7 7 7 9 b4 c1 7 243 31. i/o - - 8 8 10 c6 d2 8 246 32. i/o - - 9 9 11 a3 g6 9 249 33. i/o - - - - 12 b5 e4 10 255 34. i/o - - - - 13 b6 d1 11 258 35. i/o - - - - - d5 e3 12 261 36. i/o - - - - - d6 e2 13 267 gnd - 8 10 10 14 c7 gnd* 14 - 37. i/o - 9 11 11 15 a4 f5 15 270 38. i/o - 10 12 12 16 a5 e1 16 273 39. i/o (tms) 17 11 13 13 17 b7 f4 17 279 40. i/o 18 12 14 14 18 a6 f3 18 282 vcc ------vcc*19 - 41. i/o - - - - - d7 f2 20 285 42. i/o - - - - - d8 f1 21 291 43. i/o - - - 15 19 c8 g4 23 294 44. i/o - - - 16 20 a7 g3 24 297 45. i/o - 13 15 17 21 b8 g2 25 306 46. i/o - 14 16 18 22 a8 g1 26 309 47. i/o 19 15 17 19 23 b9 g5 27 318 48. i/o 20 16 18 20 24 c9 h3 28 321 gnd 21 17 19 21 25 d9 gnd* 29 - vcc 2218 20 22 26d10vcc*30 - 49. i/o 23 19 21 23 27 c10 h4 31 327 pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order
r xc5200 series field programmable gate arrays 7-144 november 5, 1998 (version 5.2) 50. i/o 24 20 22 24 28 b10 h5 32 330 51. i/o - 21 23 25 29 a9 j2 33 333 52. i/o - 22 24 26 30 a10 j1 34 339 53. i/o - - - 27 31 a11 j3 35 342 54. i/o - - - 28 32 c11 j4 36 345 55. i/o - - - - - d11 j5 38 351 56. i/o - - - - - d12 k1 39 354 vcc ------vcc*40 - 57. i/o 25 23 25 29 33 b11 k2 41 357 58. i/o 26 24 26 30 34 a12 k3 42 363 59. i/o - 25 27 31 35 b12 j6 43 366 60. i/o - 26 28 32 36 a13 l1 44 369 gnd - 27 29 33 37 c12 gnd* 45 - 61. i/o - - - - - d13 l2 46 375 62. i/o - - - - - d14 k4 47 378 63. i/o - - - - 38 b13 l3 48 381 64. i/o - - - - 39 a14 m1 49 387 65. i/o - - 30 34 40 a15 k5 50 390 66. i/o - - 31 35 41 c13 m2 51 393 67. i/o 27 28 32 36 42 b14 l4 52 399 68. i/o - 29 33 37 43 a16 n1 53 402 69. i/o - 30 34 38 44 b15 m3 54 405 70. i/o - 31 35 39 45 c14 n2 55 411 71. i/o 28 32 36 40 46 a17 k6 56 414 72. i/o 29 33 37 41 47 b16 p1 57 417 73. m1 (i/o) 30 34 38 42 48 c15 n3 58 426 gnd 3135 39 43 49d15gnd*59 - 74. m0 (i/o) 32 36 40 44 50 a18 p2 60 429 vcc 3337 41 45 55d16vcc*61 - 75. m2 (i/o) 34 38 42 46 56 c16 m4 62 432 76. gck2 (i/o) 35 39 43 47 57 b17 r2 63 435 77. i/o (hdc) 36 40 44 48 58 e16 p3 64 444 78. i/o - 41 45 49 59 c17 l5 65 447 79. i/o - 42 46 50 60 d17 n4 66 450 80. i/o - 43 47 51 61 b18 r3 67 456 81. i/o (ldc) 37 44 48 52 62 e17 p4 68 459 82. i/o - - 49 53 63 f16 k7 69 462 83. i/o - - 50 54 64 c18 m5 70 468 84. i/o - - - - 65 d18 r4 71 471 85. i/o - - - - 66 f17 n5 72 474 86. i/o - - - - - e15 p5 73 480 87. i/o - - - - - f15 l6 74 483 gnd - 45 51 55 67 g16 gnd* 75 - 88. i/o - 46 52 56 68 e18 r5 76 486 89. i/o - 47 53 57 69 f18 m6 77 492 90. i/o 38 48 54 58 70 g17 n6 78 495 91. i/o 39 49 55 59 71 g18 p6 79 504 vcc ------vcc*80 - 92. i/o - - - 60 72 h16 r6 81 507 93. i/o - - - 61 73 h17 m7 82 510 94. i/o - - - - - g15 n7 84 516 pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order
r november 5, 1998 (version 5.2) 7-145 xc5200 series field programmable gate arrays 7 95. i/o - - - - - h15 p7 85 519 96. i/o - 50 56 62 74 h18 r7 86 522 97. i/o - 51 57 63 75 j18 l7 87 528 98. i/o 40 52 58 64 76 j17 n8 88 531 99. i/o (err , init ) 41 53 59 65 77 j16 p8 89 534 vcc 42 54 60 66 78 j15 vcc* 90 - gnd 43 55 61 67 79 k15 gnd* 91 - 100. i/o 44 56 62 68 80 k16 l8 92 540 101. i/o 45 57 63 69 81 k17 p9 93 543 102. i/o - 58 64 70 82 k18 r9 94 546 103. i/o - 59 65 71 83 l18 n9 95 552 104. i/o - - - 72 84 l17 m9 96 555 105. i/o - - - 73 85 l16 l9 97 558 106. i/o - - - - - l15 r10 99 564 107. i/o - - - - - m15 p10 100 567 vcc ------vcc*101 - 108. i/o 46 60 66 74 86 m18 n10 102 570 109. i/o 47 61 67 75 87 m17 k9 103 576 110. i/o - 62 68 76 88 n18 r11 104 579 111. i/o - 63 69 77 89 p18 p11 105 588 gnd - 64 70 78 90 m16 gnd* 106 - 112. i/o - - - - - n15 m10 107 591 113. i/o - - - - - p15 n11 108 600 114. i/o - - - - 91 n17 r12 109 603 115. i/o - - - - 92 r18 l10 110 606 116. i/o - - 71 79 93 t18 p12 111 612 117. i/o - - 72 80 94 p17 m11 112 615 118. i/o 48 65 73 81 95 n16 r13 113 618 119. i/o 49 66 74 82 96 t17 n12 114 624 120. i/o - 67 75 83 97 r17 p13 115 627 121. i/o - 68 76 84 98 p16 k10 116 630 122. i/o 50 69 77 85 99 u18 r14 117 636 123. i/o 51 70 78 86 100 t16 n13 118 639 gnd 52 71 79 87 101 r16 gnd* 119 - done 53 72 80 88 103 u17 p14 120 - vcc 54 73 81 89 106 r15 vcc* 121 - prog 55 74 82 90 108 v18 m12 122 - 124. i/o (d7) 56 75 83 91 109 t15 p15 123 648 125. gck3 (i/o) 57 76 84 92 110 u16 n14 124 651 126. i/o - 77 85 93 111 t14 l11 125 660 127. i/o - 78 86 94 112 u15 m13 126 663 128. i/o - - - - - r14 n15 127 666 129. i/o - - - - - r13 m14 128 672 130. i/o (d6) 58 79 87 95 113 v17 j10 129 675 131. i/o - 80 88 96 114 v16 l12 130 678 132. i/o - - 89 97 115 t13 m15 131 684 133. i/o - - 90 98 116 u14 l13 132 687 134. i/o - - - - 117 v15 l14 133 690 135. i/o - - - - 118 v14 k11 134 696 gnd - 81 91 99 119 t12 gnd* 135 - 136. i/o - - - - - r12 l15 136 699 pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order
r xc5200 series field programmable gate arrays 7-146 november 5, 1998 (version 5.2) 137. i/o - - - - - r11 k12 137 708 138. i/o - 82 92 100 120 u13 k13 138 711 139. i/o - 83 93 101 121 v13 k14 139 714 vcc ------vcc*140 - 140. i/o (d5) 59 84 94 102 122 u12 k15 141 720 141. i/o (cs0 ) 60 85 95 103 123 v12 j12 142 723 142. i/o - - - 104 124 t11 j13 144 726 143. i/o - - - 105 125 u11 j14 145 732 144. i/o - 86 96 106 126 v11 j15 146 735 145. i/o - 87 97 107 127 v10 j11 147 738 146. i/o (d4) 61 88 98 108 128 u10 h13 148 744 147. i/o 62 89 99 109 129 t10 h14 149 747 vcc 63 90 100 110 130 r10 vcc* 150 - gnd 64 91 101 111 131 r9 gnd* 151 - 148. i/o (d3) 65 92 102 112 132 t9 h12 152 756 149. i/o (rs ) 66 93 103 113 133 u9 h11 153 759 150. i/o - 94 104 114 134 v9 g14 154 768 151. i/o - 95 105 115 135 v8 g15 155 771 152. i/o - - - 116 136 u8 g13 156 780 153. i/o - - - 117 137 t8 g12 157 783 154. i/o (d2) 67 96 106 118 138 v7 g11 159 786 155. i/o 68 97 107 119 139 u7 f15 160 792 vcc ------vcc*161 - 156. i/o - 98 108 120 140 v6 f14 162 795 157. i/o - 99 109 121 141 u6 f13 163 798 158. i/o - - - - - r8 g10 164 804 159. i/o - - - - - r7 e15 165 807 gnd - 100 110 122 142 t7 gnd* 166 - 160. i/o - - - - - r6 e14 167 810 161. i/o - - - - - r5 f12 168 816 162. i/o - - - - 143 v5 e13 169 819 163. i/o - - - - 144 v4 d15 170 822 164. i/o - - 111 123 145 u5 f11 171 828 165. i/o - - 112 124 146 t6 d14 172 831 166. i/o (d1) 69 101 113 125 147 v3 e12 173 834 167. i/o (rclk-busy /rdy) 70 102 114 126 148 v2 c15 174 840 168. i/o - 103 115 127 149 u4 d13 175 843 169. i/o - 104 116 128 150 t5 c14 176 846 170. i/o (d0, din) 71 105 117 129 151 u3 f10 177 855 171. i/o (dout) 72 106 118 130 152 t4 b15 178 858 cclk 73 107 119 131 153 v1 c13 179 - vcc 74 108 120 132 154 r4 vcc* 180 - 172. i/o (tdo) 75 109 121 133 159 u2 a15 181 - gnd 76 110 122 134 160 r3 gnd* 182 - 173. i/o (a0, ws ) 77 111 123 135 161 t3 a14 183 9 174. gck4 (a1, i/o) 78 112 124 136 162 u1 b13 184 15 175. i/o - 113 125 137 163 p3 e11 185 18 176. i/o - 114 126 138 164 r2 c12 186 21 177. i/o (cs1, a2) 79 115 127 139 165 t2 a13 187 27 178. i/o (a3) 80 116 128 140 166 n3 b12 188 30 179. i/o - - - - - p4 f9 189 33 pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order
r november 5, 1998 (version 5.2) 7-147 xc5200 series field programmable gate arrays 7 additional no connect (n.c.) connections for pq208 and pq240 packages notes: * pins labeled vcc* are internally bonded to a vcc plane within the bg225 package. the external pins are: b2, d8, h15, r8, b14, r1, h1, and r15. pins labeled gnd* are internally bonded to a ground plane within the bg225 package. the external pins are: a1, d12, g7, g9, h6, h8, h10, j8, k8, a8, f8, g8, h2, h7, h9, j7, j9, m8. boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 1056 = bscan.upd pin locations for xc5215 devices the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc5200 series data sheet for availability information. 180. i/o - - - - - n4 d11 190 39 181. i/o - 117 129 141 167 p2 a12 191 42 182. i/o - - 130 142 168 t1 c11 192 45 183. i/o - - - - 169 r1 b11 193 51 184. i/o - - - - 170 n2 e10 194 54 - ------gnd* - gnd - 118 131 143 171 m3 - 196 - 185. i/o - 119 132 144 172 p1 a11 197 57 186. i/o - 120 133 145 173 n1 d10 198 66 187. i/o - - - - - m4 c10 199 69 188. i/o - - - - - l4 b10 200 75 vcc ------vcc*201 - 189. i/o (a4) 81 121 134 146 174 m2 a10 202 78 190. i/o (a5) 82 122 135 147 175 m1 d9 203 81 191. i/o - - - 148 176 l3 c9 205 87 192. i/o - - 136 149 177 l2 b9 206 90 193. i/o - 123 137 150 178 l1 a9 207 93 194. i/o - 124 138 151 179 k1 e9 208 99 195. i/o (a6) 83 125 139 152 180 k2 c8 209 102 196. i/o (a7) 84 126 140 153 181 k3 b8 210 105 gnd 1 127 141 154 182 k4 gnd* 211 - pq208 pq240 1 53 105 157 208 22 143 219 354107158 37 158 51 102 155 206 83 195 52 104 156 207 98 204 pin description pc84 tq144 pq160 tq176 pq208 pg223 bg225 pq240 boundary scan order pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order vcc 142 183 212 k1 vcc* vcc* - 1. i/o (a8) 143 184 213 k2 e8 d14 138 2. i/o (a9) 144 185 214 k3 b7 c14 141 3. i/o 145 186 215 k5 a7 a15 147 4. i/o 146 187 216 k4 c7 b15 150 5. i/o - 188 217 j1 d7 c15 153 6. i/o - 189 218 j2 e7 d15 159 7. i/o (a10) 147 190 220 h1 a6 a16 162
r xc5200 series field programmable gate arrays 7-148 november 5, 1998 (version 5.2) 8. i/o (a11) 148 191 221 j3 b6 b16 165 9. i/o - - - h2 - c17 171 10. i/o - - - g1 - b18 174 vcc - - 222 e1 vcc* vcc* - 11. i/o - - 223 h3 c6 c18 177 12. i/o - - 224 g2 f7 d17 183 13. i/o 149 192 225 h4 a5 a20 186 14. i/o 150 193 226 f2 b5 b19 189 gnd 151 194 227 f1 gnd* gnd* - 15. i/o - - - h5 - c19 195 16. i/o - - - g3 - d18 198 17. i/o - 195 228 d1 d6 a21 201 18. i/o - 196 229 g4 c5 b20 207 19. i/o 152 197 230 e2 a4 c20 210 20. i/o 153 198 231 f3 e6 b21 213 21. i/o (a12) 154 199 232 g5 b4 b22 219 22. i/o (a13) 155 200 233 c1 d5 c21 222 23. i/o - - - f4 - d20 225 24. i/o - - - e3 - a23 234 25. i/o - - 234 d2 a3 d21 237 26. i/o - - 235 c2 c4 c22 243 27. i/o 156 201 236 f5 b3 b24 246 28. i/o 157 202 237 e4 f6 c23 249 29. i/o (a14) 158 203 238 d3 a2 d22 258 30. i/o (a15) 159 204 239 c3 c3 c24 261 vcc 160 205 240 a2 vcc* vcc* - gnd 1 2 1 b1 gnd* gnd* - 31. gck1 (a16, i/o) 2 4 2 d4 d4 d23 270 32. i/o (a17) 3 5 3 b2 b1 c25 273 33. i/o 4 6 4 b3 c2 d24 279 34. i/o 5 7 5 e6 e5 e23 282 35. i/o (tdi) 6 8 6 d5 d3 c26 285 36. i/o (tck) 7 9 7 c4 c1 e24 294 37. i/o - - - a3 - f24 297 38. i/o - - - d6 - e25 303 39. i/o 8 10 8 e7 d2 d26 306 40. i/o 9 11 9 b4 g6 g24 309 41. i/o - 12 10 c5 e4 f25 315 42. i/o - 13 11 a4 d1 f26 318 43. i/o - - 12 d7 e3 h23 321 44. i/o - - 13 c6 e2 h24 327 45. i/o - - - e8 - g25 330 46. i/o - - - b5 - g26 333 gnd 10 14 14 a5 gnd* gnd* - 47. i/o 11 15 15 b6 f5 j23 339 48. i/o 12 16 16 d8 e1 j24 342 49. i/o (tms) 13 17 17 c7 f4 h25 345 50. i/o 14 18 18 b7 f3 k23 351 vcc - - 19 a6 vcc* vcc* - 51. i/o - - 20 c8 f2 l24 354 52. i/o - - 21 e9 f1 k25 357 53. i/o - - - b8 - l25 363 pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r november 5, 1998 (version 5.2) 7-149 xc5200 series field programmable gate arrays 7 54. i/o - - - a8 - l26 366 55. i/o - 19 23 c9 g4 m23 369 56. i/o - 20 24 b9 g3 m24 375 57. i/o 15 21 25 e10 g2 m25 378 58. i/o 16 22 26 a9 g1 m26 381 59. i/o 17 23 27 d10 g5 n24 390 60. i/o 18 24 28 c10 h3 n25 393 gnd 19 25 29 a10 gnd* gnd* - vcc 20 26 30 a11 vcc* vcc* - 61. i/o 21 27 31 b10 h4 n26 399 62. i/o 22 28 32 b11 h5 p25 402 63. i/o 23 29 33 c11 j2 p23 405 64. i/o 24 30 34 e11 j1 p24 411 65. i/o - 31 35 d11 j3 r26 414 66. i/o - 32 36 a12 j4 r25 417 67. i/o - - - b12 - r24 423 68. i/o - - - a13 - r23 426 69. i/o - - 38 e12 j5 t26 429 70. i/o - - 39 b13 k1 t25 435 vcc - - 40 a16 vcc* vcc* - 71. i/o 25 33 41 a14 k2 u24 438 72. i/o 26 34 42 c13 k3 v25 441 73. i/o 27 35 43 b14 j6 v24 447 74. i/o 28 36 44 d13 l1 u23 450 gnd 29 37 45 a15 gnd* gnd* - 75. i/o - - - b15 - y26 453 76. i/o - - - e13 - w25 459 77. i/o - - 46 c14 l2 w24 462 78. i/o - - 47 a17 k4 v23 465 79. i/o - 38 48 d14 l3 aa26 471 80. i/o - 39 49 b16 m1 y25 474 81. i/o 30 40 50 c15 k5 y24 477 82. i/o 31 41 51 e14 m2 aa25 483 83. i/o - - - a18 - ab25 486 84. i/o - - - d15 - aa24 489 85. i/o 32 42 52 c16 l4 y23 495 86. i/o 33 43 53 b17 n1 ac26 498 87. i/o 34 44 54 b18 m3 aa23 501 88. i/o 35 45 55 e15 n2 ab24 507 89. i/o 36 46 56 d16 k6 ad25 510 90. i/o 37 47 57 c17 p1 ac24 513 91. m1 (i/o) 38 48 58 a20 n3 ab23 522 gnd 39 49 59 a19 gnd* gnd* - 92. m0 (i/o) 40 50 60 c18 p2 ad24 525 vcc 41 55 61 b20 vcc* vcc* - 93. m2 (i/o) 42 56 62 d17 m4 ac23 528 94. gck2 (i/o) 43 57 63 b19 r2 ae24 531 95. i/o (hdc) 44 58 64 c19 p3 ad23 540 96. i/o 45 59 65 f16 l5 ac22 543 97. i/o 46 60 66 e17 n4 af24 546 98. i/o 47 61 67 d18 r3 ad22 552 99. i/o (ldc) 48 62 68 c20 p4 ae23 555 pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r xc5200 series field programmable gate arrays 7-150 november 5, 1998 (version 5.2) 100. i/o - - - f17 - ae22 558 101. i/o - - - g16 - af23 564 102. i/o 49 63 69 d19 k7 ad20 567 103. i/o 50 64 70 e18 m5 ae21 570 104. i/o - 65 71 d20 r4 af21 576 105. i/o - 66 72 g17 n5 ac19 579 106. i/o - - 73 f18 p5 ad19 582 107. i/o - - 74 h16 l6 ae20 588 108. i/o - - - e19 - af20 591 109. i/o - - - f19 - ac18 594 gnd 51 67 75 e20 gnd* gnd* - 110. i/o 52 68 76 h17 r5 ad18 600 111. i/o 53 69 77 g18 m6 ae19 603 112. i/o 54 70 78 g19 n6 ac17 606 113. i/o 55 71 79 h18 p6 ad17 612 vcc - - 80 f20 vcc* vcc* - 114. i/o - 72 81 j16 r6 ae17 615 115. i/o - 73 82 g20 m7 ae16 618 116. i/o - - - h20 - af16 624 117. i/o - - - j18 - ac15 627 118. i/o - - 84 j19 n7 ad15 630 119. i/o - - 85 k16 p7 ae15 636 120. i/o 56 74 86 j20 r7 af15 639 121. i/o 57 75 87 k17 l7 ad14 642 122. i/o 58 76 88 k18 n8 ae14 648 123. i/o (err , init ) 59 77 89 k19 p8 af14 651 vcc 60 78 90 l20 vcc* vcc* - gnd 61 79 91 k20 gnd* gnd* - 124. i/o 62 80 92 l19 l8 ae13 660 125. i/o 63 81 93 l18 p9 ac13 663 126. i/o 64 82 94 l16 r9 ad13 672 127. i/o 65 83 95 l17 n9 af12 675 128. i/o - 84 96 m20 m9 ae12 678 129. i/o - 85 97 m19 l9 ad12 684 130. i/o - - - n20 - ac12 687 131. i/o - - - m18 - af11 690 132. i/o - - 99 n19 r10 ae11 696 133. i/o - - 100 p20 p10 ad11 699 vcc - - 101 t20 vcc* vcc* - 134. i/o 66 86 102 n18 n10 ae9 702 135. i/o 67 87 103 p19 k9 ad9 708 136. i/o 68 88 104 n17 r11 ac10 711 137. i/o 69 89 105 r19 p11 af7 714 gnd 70 90 106 r20 gnd* gnd* - 138. i/o - - - n16 - ae8 720 139. i/o - - - p18 - ad8 723 140. i/o - - 107 u20 m10 ac9 726 141. i/o - - 108 p17 n11 af6 732 142. i/o - 91 109 t19 r12 ae7 735 143. i/o - 92 110 r18 l10 ad7 738 144. i/o 71 93 111 p16 p12 ae6 744 145. i/o 72 94 112 v20 m11 ae5 747 pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r november 5, 1998 (version 5.2) 7-151 xc5200 series field programmable gate arrays 7 146. i/o - - - r17 - ad6 750 147. i/o - - - t18 - ac7 756 148. i/o 73 95 113 u19 r13 af4 759 149. i/o 74 96 114 v19 n12 af3 768 150. i/o 75 97 115 r16 p13 ad5 771 151. i/o 76 98 116 t17 k10 ae3 774 152. i/o 77 99 117 u18 r14 ad4 780 153. i/o 78 100 118 x20 n13 ac5 783 gnd 79 101 119 w20 gnd* gnd* - done 80 103 120 v18 p14 ad3 - vcc 81 106 121 x19 vcc* vcc* - prog 82 108 122 u17 m12 ac4 - 154. i/o (d7) 83 109 123 w19 p15 ad2 792 155. gck3 (i/o) 84 110 124 w18 n14 ac3 795 156. i/o 85 111 125 t15 l11 ab4 804 157. i/o 86 112 126 u16 m13 ad1 807 158. i/o - - 127 v17 n15 aa4 810 159. i/o - - 128 x18 m14 aa3 816 160. i/o - - - u15 - ab2 819 161. i/o - - - t14 - ac1 828 162. i/o (d6) 87 113 129 w17 j10 y3 831 163. i/o 88 114 130 v16 l12 aa2 834 164. i/o 89 115 131 x17 m15 aa1 840 165. i/o 90 116 132 u14 l13 w4 843 166. i/o - 117 133 v15 l14 w3 846 167. i/o - 118 134 t13 k11 y2 852 168. i/o - - - w16 - y1 855 169. i/o - - - w15 - v4 858 gnd 91 119 135 x16 gnd* gnd* - 170. i/o - - 136 u13 l15 v3 864 171. i/o - - 137 v14 k12 w2 867 172. i/o 92 120 138 w14 k13 u4 870 173. i/o 93 121 139 v13 k14 u3 876 vcc - - 140 x15 vcc* vcc* - 174. i/o (d5) 94 122 141 t12 k15 v2 879 175. i/o (cs0 ) 95 123 142 x14 j12 v1 882 176. i/o - - - x13 - t1 888 177. i/o - - - v12 - r4 891 178. i/o - 124 144 w12 j13 r3 894 179. i/o - 125 145 t11 j14 r2 900 180. i/o 96 126 146 x12 j15 r1 903 181. i/o 97 127 147 u11 j11 p3 906 182. i/o (d4) 98 128 148 v11 h13 p2 912 183. i/o 99 129 149 w11 h14 p1 915 vcc 100 130 150 x10 vcc* vcc* - gnd 101 131 151 x11 gnd* gnd* - 184. i/o (d3) 102 132 152 w10 h12 n2 924 185. i/o (rs ) 103 133 153 v10 h11 n4 927 186. i/o 104 134 154 t10 g14 n3 936 187. i/o 105 135 155 u10 g15 m1 939 188. i/o - 136 156 x9 g13 m2 942 189. i/o - 137 157 w9 g12 m3 948 pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r xc5200 series field programmable gate arrays 7-152 november 5, 1998 (version 5.2) 190. i/o - - - x8 - m4 951 191. i/o - - - v9 - l1 954 192. i/o (d2) 106 138 159 w8 g11 j1 960 193. i/o 107 139 160 x7 f15 k3 963 vcc - - 161 x5 vcc* vcc* 194. i/o 108 140 162 v8 f14 j2 966 195. i/o 109 141 163 w7 f13 j3 972 196. i/o - - 164 u8 g10 k4 975 197. i/o - - 165 w6 e15 g1 978 gnd 110 142 166 x6 gnd* gnd* 198. i/o - - - t8 - h2 984 199. i/o - - - v7 - h3 987 200. i/o - - 167 x4 e14 j4 990 201. i/o - - 168 u7 f12 f1 996 202. i/o - 143 169 w5 e13 g2 999 203. i/o - 144 170 v6 d15 g3 1002 204. i/o 111 145 171 t7 f11 f2 1008 205. i/o 112 146 172 x3 d14 e2 1011 206. i/o (d1) 113 147 173 u6 e12 f3 1014 207. i/o (rclk-busy /rdy) 114 148 174 v5 c15 g4 1020 208. i/o - - - w4 - d2 1023 209. i/o - - - w3 - f4 1032 210. i/o 115 149 175 t6 d13 e3 1035 211. i/o 116 150 176 u5 c14 c2 1038 212. i/o (d0, din) 117 151 177 v4 f10 d3 1044 213. i/o (dout) 118 152 178 x1 b15 e4 1047 cclk 119 153 179 v3 c13 c3 - vcc 120 154 180 w1 vcc* vcc* - 214. i/o (tdo) 121 159 181 u4 a15 d4 0 gnd 122 160 182 x2 gnd* gnd* - 215. i/o (a0, ws ) 123 161 183 w2 a14 b3 9 216. gck4 (a1, i/o) 124 162 184 v2 b13 c4 15 217. i/o 125 163 185 r5 e11 d5 18 218. i/o 126 164 186 t4 c12 a3 21 219. i/o (a2, cs1) 127 165 187 u3 a13 d6 27 220. i/o (a3) 128 166 188 v1 b12 c6 30 221. i/o - - - r4 - b5 33 222. i/o - - - p5 - a4 39 223. i/o - - 189 u2 f9 c7 42 224. i/o - - 190 t3 d11 b6 45 225. i/o 129 167 191 u1 a12 a6 51 226. i/o 130 168 192 p4 c11 d8 54 227. i/o - 169 193 r3 b11 b7 57 228. i/o - 170 194 n5 e10 a7 63 229. i/o - - 195 t2 - d9 66 230. i/o - - - r2 - c9 69 gnd 131 171 196 t1 gnd* gnd* - 231. i/o 132 172 197 n4 a11 b8 75 232. i/o 133 173 198 p3 d10 d10 78 233. i/o - - 199 p2 c10 c10 81 234. i/o - - 200 n3 b10 b9 87 vcc - - 201 r1 vcc* vcc* - pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r november 5, 1998 (version 5.2) 7-153 xc5200 series field programmable gate arrays 7 additional no connect (n.c.) connections for hq208 and hq240 packages notes: * pins labeled vcc* are internally bonded to a vcc plane within the bg225 and bg352 packages. the external pins for the bg225 are: b2, d8, h15, r8, b14, r1, h1, and r15. the external pins for the bg352 are: a10, a17, b2, b25, d13, d19, d7, g23, h4, k1, k26, n23, p4, u1, u26, w23, y4, ac14, ac20, ac8, ae2, ae25, af10, and af17. pins labeled gnd* are internally bonded to a ground plane within the bg225 and bg352 packages. the external pins for the bg225 are: a1, d12, g7, g9, h6, h8, h10, j8, k8, a8, f8, g8, h2, h7, h9, j7, j9, m8. the external pins for the bg352 are: a1, a2, a5, a8, a14, a19, a22, a25, a26, b1, b26, e1, e26, h1, h26, n1, p26, w1, w26, ab1, ab26, ae1, ae26, af1, af13, af19, af2, af22, af25, af26, af5, af8. boundary scan bit 0 = tdo.t boundary scan bit 1 = tdo.o boundary scan bit 1056 = bscan.upd 235. i/o - - - m5 - b11 90 236. i/o - - - p1 - a11 93 237. i/o (a4) 134 174 202 n1 a10 d12 99 238. i/o (a5) 135 175 203 m3 d9 c12 102 239. i/o - 176 205 m2 c9 b12 105 240. i/o 136 177 206 l5 b9 a12 111 241. i/o 137 178 207 m1 a9 c13 114 242. i/o 138 179 208 l4 e9 b13 117 243. i/o (a6) 139 180 209 l3 c8 a13 126 244. i/o (a7) 140 181 210 l2 b8 b14 129 gnd 141 182 211 l1 gnd* gnd* - hq208 hq240 206 102 219 207 104 22 208 105 37 1 107 83 3 155 98 51 156 143 52 157 158 53 158 204 54 - - pin description pq160 hq208 hq240 pg299 bg225 bg352 boundary scan order
r xc5200 series field programmable gate arrays 7-154 november 5, 1998 (version 5.2) product availability user i/o per package ordering information pins 64 84 100 100 144 156 160 176 191 208 208 223 225 240 240 299 352 type plast. vqfp plast. plcc plast. pqfp plast. vqfp plast. tqfp ceram. pga plast. pqfp plast. tqfp ceram. pga high-perf. qfp plast. pqfp ceram. pga plast. bga high-perf. qfp plast. pqfp ceram. pga plast. bga code vq64* pc84 pq100 vq100 tq144 pg156 pq160 tq176 pg191 hq208 pq208 pg223 bg225 hq240 pq240 pg299 bg352 xc5202 -6 ci ci ci ci ci ci -5 ci ci ci ci ci ci -4cccccc -3cccccc xc5204 -6 ci ci ci ci ci ci -5 ci ci ci ci ci ci -4 cccccc -3 cccccc xc5206 -6 ci ci ci ci ci ci ci ci -5 ci ci ci ci ci ci ci ci -4 cccc ccc c -3 cccc ccc c xc5210 -6 ci ci ci ci ci ci ci ci -5 ci ci ci ci ci ci ci ci -4 c c cc ccc c -3 c c cc ccc c xc5215 -6 ci ci ci ci ci ci -5 cccccc -4 cccccc -3 cccccc 7/8/98 c = commercial t j = 0 to +85 c i= industrial t j = -40 c to +100 c * vq64 package supports master serial, slave serial, and express configuration modes only. device max i/o package type vq64 pc84 pq100 vq100 tq144 pg156 pq160 tq176 pg191 hq208 pq208 pg223 bg225 hq240 pq240 pg299 bg352 xc5202 84 52 65 81 81 84 84 xc5204 124 65 81 81 117 124 124 xc5206 148 65 81 81 117 133 148 148 148 xc5210 196 65 117 133 149 164 196 196 196 xc5215 244 133 164 196 197 244 244 7/8/98 xc5210-6pq208c package type number of pins temperature range speed grade device type example:
r november 5, 1998 (version 5.2) 7-155 xc5200 series field programmable gate arrays 7 revisions version description 12/97 rev 5.0 added -3, -4 specification 7/98 rev 5.1 added spartan family to comparison, removed hq304 1 1 / 9 8 r e v 5 . 2 all specifications made final.

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